公开(公告)号：US09571043B1

公开(公告)日：2017-02-14

申请号：US14872328

申请日：2015-10-01

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd

Inventor： Richard Lum ,  Hui Fung Sim

IPC: H03F1/02 ,  H03F1/30 ,  H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45977 ,  H03F2203/45288 ,  H03F2203/45514 ,  H03F2203/45551

Abstract: An amplification system, circuit, and method of performing offset cancellation are described. The disclosed amplification system is described as including a main amplifier circuit that receives an input signal and produces an output signal, a two-phase output sampler, and an offset correction circuit. The two-phase output sample samples the output signal of the main amplifier circuit in two different clock domains and determines a delta between the samples. The delta is used to assist the offset correction circuit in generating an offset correction feedback for the main amplifier circuit.

Abstract translation: 描述了执行偏移消除的放大系统，电路和方法。 所公开的放大系统被描述为包括接收输入信号并产生输出信号的主放大器电路，两相输出采样器和偏移校正电路。 两相输出采样将主放大器电路的输出信号采样在两个不同的时钟域中，并确定采样之间的增量。 增量用于辅助偏移校正电路为主放大器电路产生偏移校正反馈。

公开(公告)号：US20170040963A1

公开(公告)日：2017-02-09

申请号：US15229756

申请日：2016-08-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Kumar GUPTA ,  Peng CAO

IPC: H03F3/26 ,  H03F3/21 ,  H03F3/45

CPC classification number: H03F3/211 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2203/45288

Abstract: An operational amplifier includes an output stage, an input stage, a first auxiliary amplifier, and a second auxiliary amplifier. The output stage includes a first output transistor and a second output transistor. The input stage is configured to drive the output stage. The first auxiliary amplifier is coupled to an output of the input stage and to an input of the first output transistor. The first auxiliary amplifier is configured to bias the first output transistor for class AB operation and to isolate the input stage from a bias voltage applied to the first output transistor. The second auxiliary amplifier is coupled to the output of the input stage and to an input of the second output transistor. The second auxiliary amplifier is configured to bias the second output transistor for class AB operation, and to isolate the input stage from a bias voltage applied to the second output transistor.

Abstract translation: 运算放大器包括输出级，输入级，第一辅助放大器和第二辅助放大器。 输出级包括第一输出晶体管和第二输出晶体管。 输入级配置为驱动输出级。 第一辅助放大器耦合到输入级的输出端和第一输出晶体管的输入端。 第一辅助放大器被配置为偏置用于AB类操作的第一输出晶体管，并且将输入级与施加到第一输出晶体管的偏置电压隔离。 第二辅助放大器耦合到输入级的输出端和第二输出晶体管的输入端。 第二辅助放大器被配置为偏置用于AB类操作的第二输出晶体管，并且将输入级与施加到第二输出晶体管的偏置电压隔离。

公开(公告)号：US09526436B2

公开(公告)日：2016-12-27

申请号：US14729339

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: H03F3/187 ,  A61B5/0482 ,  H03F1/02 ,  H03F3/45

CPC classification number: H01L29/78624 ,  A61B5/0482 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845 ,  H03F1/0205 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45118 ,  H03F2203/45288

Abstract: Neural signal amplifiers include an operational amplifier and a feedback network coupled between an output and an input thereof. The feedback network includes a tunnel field effect transistor (“TFET”) pseudo resistor that exhibits bi-directional conductivity. A drain region of the TFET may be electrically connected to the gate electrode thereof to provide a bi-directional resistor having good symmetry in terms of resistance as a function of voltage polarity.

Abstract translation: 神经信号放大器包括耦合在输出端和输入端之间的运算放大器和反馈网络。 反馈网络包括呈现双向导电性的隧道场效应晶体管（“TFET”）伪电阻器。 TFET的漏极区域可以电连接到其栅电极，以提供作为电压极性的函数的电阻方面具有良好对称性的双向电阻器。

公开(公告)号：US20160373078A1

公开(公告)日：2016-12-22

申请号：US15251955

申请日：2016-08-30

Applicant: Luxtera, Inc.

Inventor： Brian Welch

IPC: H03F3/45 ,  G01J1/44 ,  H03F3/08

CPC classification number: H03F3/45237 ,  G01J1/44 ,  H03F1/34 ,  H03F3/087 ,  H03F3/45071 ,  H03F3/45076 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/405 ,  H03F2203/45222 ,  H03F2203/45288 ,  H03F2203/45511 ,  H03F2203/45526

Abstract: A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.

Abstract translation: 公开了一种具有低于40khz低频截止的反馈跨阻放大器的系统，并且可以包括利用具有包括源极跟随器和反馈电阻器的反馈路径的跨阻抗放大器（TIA）放大经由耦合电容器接收的电信号。 反馈路径可以在TIA输入端处的耦合电容器之前耦合。 在耦合电容器之前，电压可能会发生电平偏移，以确保TIA稳定的偏置条件。 TIA可以集成在CMOS芯片中，源极跟随器可以包括CMOS晶体管。 TIA可以接收电流模式逻辑或电压信号。 电信号可以从光电检测器接收，光电检测器可以包括硅锗光电二极管，并且可以与TIA差分耦合。 芯片可以包括CMOS光子芯片，其中可以经由一个或多个光纤接收CMOS光子芯片中的光电检测器的光信号。

公开(公告)号：US20160327657A1

公开(公告)日：2016-11-10

申请号：US15149303

申请日：2016-05-09

Applicant: Siemens Medical Solutions USA, Inc.

Inventor： Nan Zhang ,  Matthias J. Schmand

IPC: G01T1/24 ,  G01T1/29 ,  H03F1/34 ,  H03F3/45 ,  H03F3/19

CPC classification number: H03F1/34 ,  G01T1/2018 ,  G01T1/208 ,  H03F3/19 ,  H03F3/45475 ,  H03F2200/222 ,  H03F2200/451 ,  H03F2203/45151 ,  H03F2203/45172 ,  H03F2203/45288 ,  H03F2203/45621

Abstract: A detector system for time-of-flight (TOF) positron emission topography (PET) includes an analog silicon photomultiplier (aSiPM) configured to detect at least one photon event. The aSiPM has an anode and a cathode. A transformer has a first side electrically coupled to the aSiPM to form a low-impedance current loop between the anode and the cathode of the transformer. An impedance ratio of the transformer N reduces an effective terminal resistance of the aSiPM. An amplifier is electrically coupled to a second side of the transformer. The amplifier has negative feedback path configured to minimize the voltage swing between a non-inverting input and an inverting input. The negative feedback path reduces an effective terminal capacitance and an effective load impedance of the aSiPM.

Abstract translation: 用于飞行时间（TOF）正电子发射形貌（PET）的检测器系统包括被配置为检测至少一个光子事件的模拟硅光电倍增管（aSiPM）。 aSiPM具有阳极和阴极。 变压器具有电耦合到aSiPM的第一侧，以在变压器的阳极和阴极之间形成低阻抗电流回路。 变压器N的阻抗比降低了aSiPM的有效端电阻。 放大器电耦合到变压器的第二侧。 放大器具有负反馈路径，配置为最小化非反相输入和反相输入之间的电压摆幅。 负反馈路径降低了aSiPM的有效端子电容和有效负载阻抗。

公开(公告)号：US20160308501A1

公开(公告)日：2016-10-20

申请号：US15192151

申请日：2016-06-24

Applicant: STMicroelectronics SA

Inventor： Laurent Chabert

IPC: H03F3/45 ,  G01S7/03 ,  H03F3/193

CPC classification number: H03F3/45282 ,  G01S7/03 ,  H03D7/1433 ,  H03D7/1458 ,  H03F1/0205 ,  H03F1/0261 ,  H03F3/19 ,  H03F3/193 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45372 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/91 ,  H03F2203/30015 ,  H03F2203/45081 ,  H03F2203/45112 ,  H03F2203/45154 ,  H03F2203/45288 ,  H04B1/06

Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

公开(公告)号：US09473090B2

公开(公告)日：2016-10-18

申请号：US14550842

申请日：2014-11-21

Applicant: INPHI CORPORATION

Inventor： James Lawrence Gorecki ,  Irene Quek

IPC: H03F3/08 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00 ,  H03F1/08 ,  H03F3/30

CPC classification number: H03G3/3084 ,  H03F1/086 ,  H03F3/082 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45224 ,  H03F2203/45288 ,  H03G1/0035 ,  H04B10/2507 ,  H04B10/6911

Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

Abstract translation: 本公开涉及用于多级光通信的放大器领域，更具体地涉及具有增益控制的跨阻抗放大器（TIA）的技术。 所要求保护的实施例解决了实现具有高线性度，低噪声，低功率和宽带宽的低成本TIA的问题。 更具体地，一些权利要求涉及用于使用由反馈环路控制的多个基于逆变器的复制增益控制单元来提供TIA增益控制的方法，以管理进入放大输出级的电流，从而管理TIA输出电压。

公开(公告)号：US09444418B1

公开(公告)日：2016-09-13

申请号：US14206632

申请日：2014-03-12

Applicant: Russell D. Wyse ,  Michael L. Hageman

Inventor： Russell D. Wyse ,  Michael L. Hageman

IPC: H03F3/45 ,  H03F3/19 ,  H03G3/00

CPC classification number: H03G1/0017 ,  H03D7/1433 ,  H03D7/1458 ,  H03F3/19 ,  H03F3/191 ,  H03F3/4508 ,  H03F3/45089 ,  H03F3/45174 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2203/45018 ,  H03F2203/45024 ,  H03F2203/45054 ,  H03F2203/45154 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03G1/0023 ,  H03G1/0088 ,  H03G3/00

Abstract: A transistor cell can be modeled as a transistor with a collector, a base, and an emitter operating with a current at the collector to produce a minimum transconductance in the transistor cell that increases a current gain and improves at least one operating characteristic of the transistor cell. The operating characteristics include bandwidth, gain, and output power.

Abstract translation: 晶体管单元可以被建模为具有集电极，基极和发射极的晶体管，其在集电极处以电流工作，以在晶体管单元中产生最小跨导，从而增加电流增益并改善晶体管的至少一个工作特性 细胞。 操作特性包括带宽，增益和输出功率。

公开(公告)号：US20160261246A1

公开(公告)日：2016-09-08

申请号：US15030375

申请日：2014-09-26

Applicant: Nippon Telegraph and Telephone Corporation ,  NTT Electronics Corporation

Inventor： Hiroshi KOIZUMI ,  Masafumi NOGAWA ,  Masatoshi TOBAYASHI ,  Masahiro ENDO

IPC: H03G3/30 ,  H04B10/58 ,  H03F3/45

CPC classification number: H03G3/3084 ,  H03F3/082 ,  H03F3/087 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/408 ,  H03F2203/45142 ,  H03F2203/45212 ,  H03F2203/45288 ,  H03G3/3052 ,  H04B10/58 ,  H04B10/6931

Abstract: A transimpedance amplifier circuit (1) includes an amplifier (22) that amplifies a received signal, an automatic gain control (AGC) circuit (2) that controls the amplification gain of the amplifier by a first time constant in accordance with the level of the received signal, and a first selection circuit (25) that selects the first time constant from a plurality of predetermined values. This can simultaneously implement a short time constant of an AGC function necessary to instantaneously respond to a burst signal and a long time constant of the AGC function necessary to obtain a satisfactory bit error rate (BER) characteristic in a continuous signal by an inexpensive and compact circuit arrangement.

Abstract translation: 跨阻放大器电路（1）包括放大接收信号的放大器（22），自动增益控制（AGC）电路（2），其根据第一时间常数控制放大器的放大增益第一时间常数 以及从多个预定值中选择第一时间常数的第一选择电路（25）。 这可以同时实现瞬时响应突发信号所必需的AGC功能的短时间常数以及通过廉价且紧凑的方式在连续信号中获得令人满意的误码率（BER）特性所需的AGC功能的长时间常数 电路布置。

公开(公告)号：US09331469B2

公开(公告)日：2016-05-03

申请号：US13829366

申请日：2013-03-14

Applicant: Semiconductor Components Industries, LLC

Inventor： Riley D. Beck ,  Kent D. Layton

IPC: H02H3/16 ,  H02H3/33 ,  G01R27/18 ,  H02H1/00 ,  H02H1/04

CPC classification number: H03F1/303 ,  G01R27/18 ,  G01R31/025 ,  H02H1/0092 ,  H02H1/04 ,  H02H3/162 ,  H02H3/33 ,  H03F3/45 ,  H03F2203/45152 ,  H03F2203/45228 ,  H03F2203/45288

Abstract: A method and circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.