公开(公告)号：US07939951B2

公开(公告)日：2011-05-10

申请号：US12526242

申请日：2008-01-29

Applicant: Hirotoshi Usui

Inventor： Hirotoshi Usui

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H05K1/112 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A mounting substrate having a structure allowing reduction of the cost and an electronic apparatus formed by surface-mounting a semiconductor device thereon are provided. The mounting substrate is a mounting substrate mounted with a semiconductor device having external terminals alignedly arrayed in the form of a matrix, and includes junctions arrayed on a surface to which the semiconductor device is opposed so that the external terminals are bonded thereto respectively and wires connected to the junctions respectively and extracted out of a region to which the semiconductor device is bonded. The wires connected to inwardly arrayed 4 rows by n columns (n: integer of not less than 5) of the junctions respectively are formed on a first wiring layer. The wires connected to the junctions set in two annular arrays surrounding the outer sides of the 4 rows by n columns of junctions respectively are formed on a second wiring layer different from the first wiring layer.

Abstract translation: 提供了具有能够降低成本的结构的安装基板和通过在其上表面安装半导体器件而形成的电子设备。 安装基板是安装有半导体器件的安装基板，该半导体器件具有排列成矩阵形式的外部端子，并且包括排列在半导体器件相对的表面上的接合部，使得外部端子分别接合到其上并连接导线 并且从与半导体器件接合的区域中提取出来。 在第一布线层上分别形成连接到内部排列的4列×n列（n：不小于5的整数）的布线。 在与第一布线层不同的第二布线层上分别形成有连接在四行×n列的接点的围绕外侧的两个环状阵列的连接点的布线。

公开(公告)号：US07935896B2

公开(公告)日：2011-05-03

申请号：US12604459

申请日：2009-10-23

Applicant: Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

Inventor： Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

IPC: H05K1/11

CPC classification number: H05K1/114 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

Abstract: Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

Abstract translation: 公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。 这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。 通孔布置可以不同于衬垫布置。 通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。 可以改变通孔布置以在板的层上实现期望的布线密度。 增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。 接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。 因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。 也可以改变通孔装置以限制相邻信号导体之间的串扰。 因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

公开(公告)号：US07906835B2

公开(公告)日：2011-03-15

申请号：US11837835

申请日：2007-08-13

Applicant: Robert John Romero

Inventor： Robert John Romero

IPC: H01L23/495

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014

Abstract: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.

Abstract translation: 提供了球栅排列图案的方法，系统和装置。 球栅阵列平台图案包括多个焊盘和导电迹线。 多个接地焊盘被布置成行和列的阵列。 阵列的周边边缘包括一对相邻的长方形焊盘。 导电迹线在一对相邻的长方形焊盘之间从位于阵列内部的焊盘传送到阵列外部的位置。 长方形的焊盘比标准的圆形焊盘更窄，从而为迹线的布线提供更多的间隙。 长方形的接地焊盘使得焊盘图案阵列的更多焊盘能够在每个布线层上的阵列外部布线，从而可以节省印刷电路板部件和组装成本。

公开(公告)号：US20110019379A1

公开(公告)日：2011-01-27

申请号：US12801834

申请日：2010-06-28

Applicant: Koujirou Shibuya

Inventor： Koujirou Shibuya

IPC: H05K7/00 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0271 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

Abstract translation: 印刷电路板包括布置在允许其中安装电子部件的安装区域中的多个焊盘; 以及分别连接到特定焊盘的布线，其是最外侧设置在所有焊盘之外的最外侧焊盘中的至少一个，其中特定焊盘的连接部分和连接到特定焊盘的布线位于封闭曲线内部，该封闭曲线共同围绕 通过最短路径，形成在安装区域中的所有最外面的焊盘。

公开(公告)号：US07839652B2

公开(公告)日：2010-11-23

申请号：US12255789

申请日：2008-10-22

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H05K1/0243 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/023 ,  H05K1/112 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.

Abstract translation: 对于处理高速差分信号的诸如BGA或CSP的多端子半导体封装，将高速信号分配给插入器基板上的最内侧定位的电极焊盘，并且电极焊盘连接到 位于内插器基板上的最外侧的球垫。 通过这种布置，可以显着地减少电镀短截线的长度，并且可以最小化对信号波形的不利影响。 这种布置对于差分信号线特别有效。

公开(公告)号：US07816610B2

公开(公告)日：2010-10-19

申请号：US11853061

申请日：2007-09-11

Applicant: Ching-Chih Li

Inventor： Ching-Chih Li

IPC: H05K1/03

CPC classification number: H05K1/112 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L2924/14 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The layout circuit comprises a first 3×2 grid array and a second 3×2 grid array. The first 3×2 grid array comprises first, second and third signal contact points and the first and second fixed potential contact points are coupled to a first fixed potential. The first and second fixed potential contact points are arranged diagonally into the first 2×2 array and the first and second signal contact points are also arranged diagonally into the first 2×2 array. The second 3×2 grid array comprises fourth, fifth and sixth signal contact points and the third and fourth fixed potential contact points are coupled to the first fixed potential. The third and fourth fixed potential contact points are arranged diagonally into the second 2×2 array and the fourth and fifth signal contact points are also arranged diagonally into the second 2×2 array.

Abstract translation: 布局电路包括第一3×2网格阵列和第二3×2网格阵列。 第一3×2栅格阵列包括第一，第二和第三信号接触点，并且第一和第二固定电位接触点耦合到第一固定电位。 第一和第二固定电位接触点对角地布置在第一2×2阵列中，并且第一和第二信号接触点也对角地布置到第一2×2阵列中。 第二3×2栅格阵列包括第四，第五和第六信号接触点，第三和第四固定电位接触点耦合到第一固定电位。 第三和第四固定电位接触点对角设置在第二2×2阵列中，第四和第五信号接触点也被对角地布置到第二2×2阵列中。

公开(公告)号：US07797663B2

公开(公告)日：2010-09-14

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在μVia的外层焊盘上方的导电圆顶的微孔（μVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。

公开(公告)号：US20100195300A1

公开(公告)日：2010-08-05

申请号：US12656451

申请日：2010-01-29

Applicant: Do Hyung Kim ,  Jung-Mo Yang ,  Hyun Jung Yoo ,  Dong-Yoon Seo ,  In-Young Park

Inventor： Do Hyung Kim ,  Jung-Mo Yang ,  Hyun Jung Yoo ,  Dong-Yoon Seo ,  In-Young Park

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Disclosed is an electronic device module including a module substrate having first and second electronic device pair portions. The first electronic device pair portion may include a first and a second contact pad area and a first via area between the first and second contact pad areas. The first electronic device pair portion may also include a first layer and a second layer. The first layer may include a plurality of first lines connecting a plurality of contact pads in the first contact pad area on one side of the module substrate to a plurality of vias. The second layer may include a plurality of second lines connecting a plurality of contact pads in the second contact pad area to a plurality of vias in the via area. The second layer may also include a plurality of third lines connecting the first and second electronic device pair portions.

Abstract translation: 公开了一种电子设备模块，包括具有第一和第二电子设备对部分的模块基板。 第一电子器件对部分可以包括第一和第二接触焊盘区域和第一和第二接触焊盘区域之间的第一通孔区域。 第一电子设备对部分还可以包括第一层和第二层。 第一层可以包括将模块衬底的一侧上的第一接触焊盘区域中的多个接触焊盘连接到多个通孔的多条第一线。 第二层可以包括将第二接触焊盘区域中的多个接触焊盘连接到通孔区域中的多个通孔的多条第二线路。 第二层还可以包括连接第一和第二电子设备对部分的多条第三线。

公开(公告)号：US07759787B2

公开(公告)日：2010-07-20

申请号：US11935834

申请日：2007-11-06

Applicant: Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

Inventor： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

IPC: H01L23/053 ,  H01L23/12

CPC classification number: H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09227 ,  H05K2203/1572 ,  Y10T29/49004 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

Abstract translation: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

公开(公告)号：US20100149775A1

公开(公告)日：2010-06-17

申请号：US12584516

申请日：2009-09-08

Applicant: Sang-Ho Park ,  Sa-Yoon Kang ,  Si-Hoon Lee

Inventor： Sang-Ho Park ,  Sa-Yoon Kang ,  Si-Hoon Lee

IPC: H05K7/00

CPC classification number: H01L23/49838 ,  G02F1/13452 ,  H01L21/563 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/09227 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate.

Abstract translation: 带状电路基板包括具有第一布线的基膜和设置在基膜上的第二布线。 第一布线通过第一侧延伸到芯片安装部分中，并且在芯片安装部分内向第二侧弯曲。 第二布线通过第三侧延伸到芯片安装部分，并且在芯片安装部分内向第二侧弯曲。 第一，第二和第三面是芯片安装部分的不同侧面。 因此，通过在芯片安装部分内布置布线以使得使用带电路基板的诸如显示面板组件的电子设备的进一步小型化来使基膜的尺寸和成本进一步降低。