公开(公告)号：US09564881B2

公开(公告)日：2017-02-07

申请号：US14720634

申请日：2015-05-22

申请人： QUALCOMM Incorporated

发明人： Qi Ye ,  Steven James Dillen ,  Animesh Datta ,  Zhengyu Duan ,  Satyanarayana Sahu ,  Praveen Narendranath

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K5/131 ,  H03K5/13

CPC分类号： H03K3/0375 ,  H03K3/012 ,  H03K3/037 ,  H03K5/131

摘要： A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

摘要翻译： 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在延迟模块输出端提供功能上的I1IA，其中I1是I的函数，IA是IN0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，IN0是第一个 净输入。

公开(公告)号：US20050286320A1

公开(公告)日：2005-12-29

申请号：US11167627

申请日：2005-06-27

申请人： Keiichi Iwasaki

发明人： Keiichi Iwasaki

IPC分类号： G06F1/10 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/131 ,  H03K19/0175 ,  H03L7/07 ,  H03L7/081

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0805

摘要： A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.

摘要翻译： 延迟控制装置包括第一和第二延迟元件，每个延迟元件被配置为接收和延迟选通信号和时钟预定的延迟值。 提供规定数量的触发器，用于在接收到从第二延迟元件输出的选通信号时输入数据。 当选择装置选择选通信号时，第二延迟元件将选通信号延迟并输出到触发器。 相位比较器比较从第一和第二延迟元件输出的时钟。 当选择装置选择时钟时，延迟控制装置根据相位比较器的比较结果改变第二延迟元件的规定延迟值。

公开(公告)号：US06965259B2

公开(公告)日：2005-11-15

申请号：US10851271

申请日：2004-05-21

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： G06F1/06 ,  G06F1/08 ,  H03H17/06 ,  H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03L7/00 ,  H03L7/08 ,  H03L7/06

CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

摘要： A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

公开(公告)号：US06924679B2

公开(公告)日：2005-08-02

申请号：US09959997

申请日：2001-03-13

申请人： Katsunori Seno ,  Akihiko Hashiguchi ,  Tetsuo Kondo ,  Takahiro Seki

发明人： Katsunori Seno ,  Akihiko Hashiguchi ,  Tetsuo Kondo ,  Takahiro Seki

IPC分类号： G06F1/10 ,  G06F1/32 ,  H03K3/354 ,  H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03K5/14 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/06

CPC分类号： G06F1/324 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3296 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00026 ,  H03K2005/00078 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0996 ,  Y02D10/126 ,  Y02D10/172

摘要： A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit 11, an input signal generation circuit 12 able to change the phase difference i of a reference signal outφi and an input signal outφ0 in accordance with a control signal Si when generating the two signals from a clock, a monitor circuit 13 having a characteristic between a power supply voltage and delay the same as that of a critical path of the semiconductor circuit 11, propagating the input signal outφ0, and outputting a delayed signal outφ0′ to be delayed exactly by a time equivalent to a delay of the critical path (or smaller by a constant ratio), a delay detection circuit 14 for detecting a delay of the delayed signal outφ0′ relative to the reference signal outφi, and a power supply voltage control circuit 15 for controlling a power supply voltage VDD supplied to the semiconductor device 11 and the monitor circuit 13 based on the detection result.

摘要翻译： 一种电源电压控制装置，包括具有广泛用途的输入信号生成电路或新颖结构的小型监视电路，以及半导体电路及其驱动方法，具有半导体电路11，输入信号发生电路 12，当从时钟产生两个信号时，能够根据控制信号Si改变参考信号outphii的相位差i和输入信号outphi0，具有电源电压和延迟电源电压之间的特性的监视器电路13 与半导体电路11的关键路径相同，传播输入信号outphi 0，并输出延迟信号outphi 0'以精确地延迟等于关键路径的延迟的时间（或更小的一定比例 ），延迟检测电路14，用于检测延迟信号outphi 0'相对于参考信号outphii的延迟;以及电源电压控制电路15，用于 根据检测结果控制提供给半导体装置11和监视电路13的电源电压V DD。

公开(公告)号：US06918050B2

公开(公告)日：2005-07-12

申请号：US09773595

申请日：2001-02-02

申请人： Atsushi Yoshikawa ,  Yasuhiko Hagihara

发明人： Atsushi Yoshikawa ,  Yasuhiko Hagihara

IPC分类号： G06F1/06 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/04 ,  H03K5/131 ,  H03K5/135 ,  H03L7/081 ,  G06F1/04

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0818

摘要： The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.

摘要翻译： 本发明通过控制半导体集成电路器件中的内部寄存器值和内部信号或外部信号来提供输入信号的延迟时间间隔。 本发明包括第一门阵列10，用于通过第一开关装置40对输入信号的延迟时间间隔进行微调，连接到第一门阵列中的指定栅极的输出侧的电容60至63和70至73 至43，用于对输入信号的延迟时间间隔进行粗略调整的第二门阵列20; 以及控制装置30，其通过调整连接到第一门阵列中的指定栅极的输出侧的电容和第二栅极阵列20中的栅极级数来调节输入信号的延迟时间间隔。

公开(公告)号：US06904112B1

公开(公告)日：2005-06-07

申请号：US09617450

申请日：2000-07-17

申请人： Frank Sattler ,  Walter Klumb

发明人： Frank Sattler ,  Walter Klumb

IPC分类号： H03K5/06 ,  G06F1/10 ,  H03K5/13 ,  H03K5/131 ,  H04B15/04 ,  H04L7/04

CPC分类号： H03K5/13 ,  G06F1/10 ,  H03K5/131 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

摘要： A method for modulating a basic clock signal for digital circuits, in which distances between adjacent switching edges are altered, the basic clock signal being conducted via a changing number of delay units for altering the distances between the adjacent switching edges, the method comprising the step of calibrating delay times of the delay units (D1-Dn), wherein the delay units (D1-Dn) each have a plurality of delay elements (10) which are controlled to impart zero delay or a non-zero value of delay to a clock signal individually or in groups of the display elements; wherein the respective distance between two adjacent switching edges is derived from numbers of a random number generator; and wherein the distance between two successive switching edges is derived as a function of the random number and a modulation factor.

摘要翻译： 一种用于调制数字电路的基本时钟信号的方法，其中相邻切换边缘之间的距离被改变，基本时钟信号通过改变数量的延迟单元传导，以改变相邻切换边缘之间的距离，该方法包括步骤 校准延迟单元（D 1 -D n）的延迟时间，其中延迟单元（D 1 -Dn）各自具有多个延迟元件（10），所述延迟单元被控制以赋予零延迟或非零值的延迟 分别或组成显示元件的时钟信号; 其中两个相邻切换边缘之间的相应距离是从随机数发生器的数目导出的; 并且其中两个连续切换边缘之间的距离被导出为随机数和调制因子的函数。

公开(公告)号：US06888387B2

公开(公告)日：2005-05-03

申请号：US10371248

申请日：2003-02-20

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： G06F1/06 ,  G06F1/08 ,  H03H17/06 ,  H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03L7/00 ,  H03L7/08

CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

摘要： A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

摘要翻译： 时钟控制电路包括：控制电路102，用于在参考时钟的每个时钟周期输出用于将相位加到或减去相位的控制信号，所述参考时钟是作为输入时钟或从输入时钟产生的时钟的参考时钟， 相位调整电路101馈送输入时钟并输出相位被调整到参考时钟的输出时钟。

公开(公告)号：US20050052944A1

公开(公告)日：2005-03-10

申请号：US10965845

申请日：2004-10-18

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K5/13 ,  H03K5/131 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/107 ,  G11C8/00

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

摘要翻译： 一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间 的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域 形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。 电源通道也与其他数字电路无关地形成。

公开(公告)号：US06847243B2

公开(公告)日：2005-01-25

申请号：US10851891

申请日：2004-05-21

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： G06F1/06 ,  G06F1/08 ,  H03H17/06 ,  H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03L7/00 ,  H03L7/08

CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

摘要： A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

公开(公告)号：US6118319A

公开(公告)日：2000-09-12

申请号：US17363

申请日：1998-02-02

申请人： Toshio Yamada ,  Masashi Agata

发明人： Toshio Yamada ,  Masashi Agata

IPC分类号： G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/02 ,  H03K3/10 ,  H03K5/13 ,  H03K5/131 ,  H03K5/19 ,  H04L7/00

CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

摘要翻译： 根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出 信号。