公开(公告)号：US5523696A

公开(公告)日：1996-06-04

申请号：US163452

申请日：1993-12-07

Applicant: Richard G. Charlton ,  George C. Correla ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

Inventor： Richard G. Charlton ,  George C. Correla ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R1/07307 ,  G01R31/2886

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

Abstract translation: 公开了一种用于测试半导体芯片的方法和装置。 单个半导体芯片具有I / O触点。 该装置设置有具有对应于半导体芯片上的触点的触点的插入器。 芯片和内插器触点都可以是任何已知的类型，包括金属球，凸块或凸片，或者可以设置有树枝状表面。 首先将芯片触点与插入件上的触点进行相对松动的临时接触，然后将大于每芯片接触5克的压缩力施加到芯片上以迫使芯片触头与插入器触点良好地电接触。 然后进行芯片的测试。 测试可能包括加热芯片以及将信号应用于芯片触点。 测试后，芯片从基板上取下。

公开(公告)号：US5185073A

公开(公告)日：1993-02-09

申请号：US692606

申请日：1991-04-29

Applicant: Perminder S. Bindra ,  Jerome J. Cuomo ,  Thomas P. Gall ,  Anthony P. Ingraham ,  Sung K. Kang ,  Jungihl Kim ,  Paul Lauro ,  David N. Light ,  Voya R. Markovich ,  Ekkehard F. Miersch ,  Jaynal A. Molla ,  Douglas O. Powell ,  John J. Ritsko ,  George J. Saxenmeyer, Jr. ,  Jack A. Varcoe ,  George F. Walker

Inventor： Perminder S. Bindra ,  Jerome J. Cuomo ,  Thomas P. Gall ,  Anthony P. Ingraham ,  Sung K. Kang ,  Jungihl Kim ,  Paul Lauro ,  David N. Light ,  Voya R. Markovich ,  Ekkehard F. Miersch ,  Jaynal A. Molla ,  Douglas O. Powell ,  John J. Ritsko ,  George J. Saxenmeyer, Jr. ,  Jack A. Varcoe ,  George F. Walker

IPC: H01R4/26 ,  H01R4/58 ,  H01R13/22 ,  H05K3/32

CPC classification number: H01L24/83 ,  H01L24/90 ,  H01R13/22 ,  H01R4/26 ,  H01R4/58 ,  H05K3/325 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48227 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14

Abstract: A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. Pulse electroplating of palladium provides a dendritic deposit of uniform height, uniform rounded points and less branching. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.

Abstract translation: 提供一种用于电气设备的可分离和可重新连接的连接件，其适于小型化，其中容纳从平面部分一体地附接和突出的垂直交叉构件，以控制与相对的类似接触件配合时发生的横向位移损坏。 通过提供一个或多个共形相对的接触，通过加强涂层和基底加强件以及可变形的涂层来容纳横向应力来避免位移损伤。 接触是通过物理和化学过程制造的，包括溅射，正常和脉冲电镀以及化学气相沉积。 钯的脉冲电镀提供均匀高度，均匀圆点和较少支化的树枝状沉积物。 完成的触点设置有增强刚性的周边固定材料。

公开(公告)号：US06094059A

公开(公告)日：2000-07-25

申请号：US241045

申请日：1999-02-01

Applicant: Jerome A. Frankeny ,  Anthony P. Ingraham ,  James Steven Kamperman ,  James Robert Wilcox

Inventor： Jerome A. Frankeny ,  Anthony P. Ingraham ,  James Steven Kamperman ,  James Robert Wilcox

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2886

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.

Abstract translation: 提供了以预定图案布置的在其一个面上具有多个触点的集成电路装置，特别是晶片的测试/应力的技术。 提供具有电介质基板和器件接触面和测试器接触面的插入件。 设备触点上的第一多个可释放连接器以相同的预定图案布置，并且第二多个可释放连接器以相同的预定图案布置在测试器接触面上。 可释放的连接由枝晶形成。 导通孔分别连接第一和第二可释放连接器的相应连接器。 提供了具有也以相同的预定图案布置的多个接触垫的测试头。 在测试头上提供电路以将每个接触焊盘上的每个接触垫连接到外部引线上，以提供与测试头上的每个接触焊盘的信号接触。 插入器位于IC器件和测试头之间，IC器件上的触点与第一组多个连接器接触，测试头上的接触焊盘与第二组连接器接触。 信号从电引线提供给连接器焊盘，用于执行集成电路器件的测试和/或老化。 测试在高温下进行。 还公开了测试头结构。

公开(公告)号：US6061245A

公开(公告)日：2000-05-09

申请号：US10667

申请日：1998-01-22

Applicant: Anthony P. Ingraham ,  Glenn L. Kehley ,  Sanjeev B. Sathe ,  John R. Slack

Inventor： Anthony P. Ingraham ,  Glenn L. Kehley ,  Sanjeev B. Sathe ,  John R. Slack

IPC: H01L23/467 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  H05K1/14

CPC classification number: H01L25/065 ,  H01L23/467 ,  H01L23/5385 ,  H01L25/0657 ,  H05K1/189 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/0002

Abstract: An efficient cooling mechanism for a multi-chip carrier can be provided while conserving board surface area. Flexible circuitized material is used to form multi-chip carriers with air baffle capability. The flex is folded or curved into the desired shape and held in position with a support structure. Bonding sites for chips are located on regions through the carrier. Shapes which provide air baffle capabilities include coils, spring-like coils and serpentines.

Abstract translation: 可以在节省板表面积的同时提供多芯片载体的有效的冷却机构。 柔性电路化材料用于形成具有空气挡板能力的多芯片载体。 弯曲物被折叠或弯曲成所需的形状并且用支撑结构保持就位。 芯片的绑定位置位于通过运营商的地区。 提供空气挡板功能的形状包括线圈，弹簧状线圈和蛇纹。

公开(公告)号：US6121069A

公开(公告)日：2000-09-19

申请号：US390084

申请日：1999-09-03

Applicant: Christina M. Boyko ,  Anthony P. Ingraham ,  Voya R. Markovich ,  David J. Russell

Inventor： Christina M. Boyko ,  Anthony P. Ingraham ,  Voya R. Markovich ,  David J. Russell

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H05K3/3436 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2203/0435 ,  H05K2203/073 ,  H05K3/3463 ,  Y02P70/613

Abstract: A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

Abstract translation: 焊料互连优选地使用富铅球，以将低温芯片附接到任何更高级别的封装衬底上。 在使用标准工艺形成焊球之后，使用光致抗蚀剂形成球限制金属掩模。 使用锡水溶液浸渍法将优选纯锡的薄盖层沉积在焊球的表面上。

公开(公告)号：US5949246A

公开(公告)日：1999-09-07

申请号：US789926

申请日：1997-01-28

Applicant: Jerome A. Frankeny ,  Anthony P. Ingraham ,  James Steven Kamperman ,  James Robert Wilcox

Inventor： Jerome A. Frankeny ,  Anthony P. Ingraham ,  James Steven Kamperman ,  James Robert Wilcox

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2886

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.

公开(公告)号：US5926369A

公开(公告)日：1999-07-20

申请号：US9862

申请日：1998-01-22

Applicant: Anthony P. Ingraham ,  Glenn L. Kehley ,  Sanjeev B. Sathe ,  John R. Slack

Inventor： Anthony P. Ingraham ,  Glenn L. Kehley ,  Sanjeev B. Sathe ,  John R. Slack

IPC: H01L23/367 ,  H01L25/065 ,  H05K7/20

CPC classification number: H01L25/065 ,  H01L23/367 ,  H05K7/2049 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311

Abstract: A multi-chip carrier which uses less lateral mounting space on the surface of a circuit board or card can be formed using flexible circuitized material. Lateral space is compressed by utilizing more vertical space to package chips and components. The problem of cooling multiple chips in a tight space may be accomplished by integrating the heat sink in with the circuit carrier and having the heat sink double as a support structure. A flex material is folded or shaped. Different regions of the flex are used for mounting chips, mounting support mechanisms, or mounting the structure on a carrier or substrate.

Abstract translation: 可以使用柔性电路化材料形成在电路板或卡表面上使用较少横向安装空间的多芯片载体。 通过利用更多的垂直空间来封装芯片和部件来压缩横向空间。 在紧密空间中冷却多个芯片的问题可以通过将散热器与电路载体集成并且具有作为支撑结构的双重散热器来实现。 柔性材料折叠或成形。 柔性的不同区域用于安装芯片，安装支撑机构或将结构安装在载体或基板上。

公开(公告)号：US5528159A

公开(公告)日：1996-06-18

申请号：US454458

申请日：1995-05-30

Applicant: Richard G. Charlton ,  George C. Correia ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

Inventor： Richard G. Charlton ,  George C. Correia ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R1/07307 ,  G01R31/2886

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

公开(公告)号：US5420520A

公开(公告)日：1995-05-30

申请号：US76069

申请日：1993-06-11

Applicant: Morris Anschel ,  Anthony P. Ingraham ,  Charles R. Lamb ,  Michael D. Lowell ,  Voya R. Markovich ,  Wolfgang Mayr ,  Richard G. Murphy ,  Mark V. Pierson ,  Tamar A. Powers ,  Timothy S. Reny ,  Scott D. Reynolds ,  Bahgat G. Sammakia ,  Wayne R. Storr

Inventor： Morris Anschel ,  Anthony P. Ingraham ,  Charles R. Lamb ,  Michael D. Lowell ,  Voya R. Markovich ,  Wolfgang Mayr ,  Richard G. Murphy ,  Mark V. Pierson ,  Tamar A. Powers ,  Timothy S. Reny ,  Scott D. Reynolds ,  Bahgat G. Sammakia ,  Wayne R. Storr

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01R13/02 ,  G01R1/073 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R31/2886 ,  G01R31/2862 ,  G01R31/287 ,  G01R31/2877 ,  G01R31/2879

Abstract: A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.

Abstract translation: 公开了一种测试半导体芯片的方法。 单个半导体芯片具有I / O，电源和接地触点。 在本发明的方法中，提供了一种芯片测试夹具系统。 芯片测试夹具系统具有对应于半导体芯片上的触点的触点。 载体触点具有树枝状表面。 芯片触点与芯片测试夹具系统上的导体焊盘导电接触。 测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。 测试后，芯片从基板上取下。

公开(公告)号：US5391514A

公开(公告)日：1995-02-21

申请号：US229883

申请日：1994-04-19

Applicant: Thomas P. Gall ,  Anthony P. Ingraham

Inventor： Thomas P. Gall ,  Anthony P. Ingraham

IPC: H01L21/60 ,  H01L21/28 ,  H01L21/58

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/11462 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351

Abstract: A method of flip chip bonding an integrated circuit chip to a chip carrier. A high melting temperature composition, such as a binary Pb/Sn alloy, is deposited on contacts on, for example, the chip, and constituents of a low melting composition, such as Bi and Sn, are codeposited on contacts on, for example, the chip carrier. The chip and chip carrier are then heated. This causes the lower melting temperature composition, for example the Bi and Sn, to melt and form a low melting temperature alloy, such as a Bi/Sn alloy. The low melting alloy dissolves the higher melting composition, as Pb/Sn. This results in the formation of a solder bond of a low melting point third composition, such as a ternary alloy of Bi/Pb/Sn.

Abstract translation: 将集成电路芯片倒装芯片连接到芯片载体的方法。 将诸如二元Pb / Sn合金的高熔点组合物沉积在例如芯片上的触点上，并且诸如Bi和Sn的低熔点组合物的成分共沉积在例如， 芯片载体。 然后加热芯片和芯片载体。 这导致较低的熔融温度组合物，例如Bi和Sn熔化并形成诸如Bi / Sn合金的低熔点合金。 低熔点合金溶解较高熔点的组分，如Pb / Sn。 这导致形成低熔点第三组合物如Bi / Pb / Sn的三元合金的焊料接合。