公开(公告)号：US08481403B1

公开(公告)日：2013-07-09

申请号：US12984524

申请日：2011-01-04

申请人： Vishal Gauri ,  Raashina Humayun ,  Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

发明人： Vishal Gauri ,  Raashina Humayun ,  Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

IPC分类号： H01L21/4757

CPC分类号： H01L21/31 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/31608 ,  H01L21/76224

摘要： Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.

公开(公告)号：US07727906B1

公开(公告)日：2010-06-01

申请号：US11493679

申请日：2006-07-26

申请人： Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

发明人： Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

IPC分类号： H01L21/31

CPC分类号： C23C16/045 ,  C23C16/4404 ,  C23C16/4405 ,  H01J37/32165 ,  H01L21/31604

摘要： This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

摘要翻译： 本发明涉及用于制造诸如半导体晶片的器件的电子器件制造，并且解决了用于形成具有高纵横比，窄宽度凹陷特征的电介质层的HDP CVD设备的反应室中沉积的有害氟负载效应，具有重复的dep / etch / dep进程。 通过采用钝化处理的方法和在处理基板之前对涂层进行涂布，在沉积均匀性方面降低了室中对有害的氟负载效应并提供具有较小沉积厚度变化的晶片。 在优选的方法中，在批次的每个晶片完成之后，重复钝化步骤。 在另一优选方法中，在批料的所有晶片完成之后，重复钝化和预涂步骤。 优选的钝化气体是氢和氧的混合物。

公开(公告)号：US20090130837A1

公开(公告)日：2009-05-21

申请号：US12345431

申请日：2008-12-29

申请人： Judy H. Huang

发明人： Judy H. Huang

IPC分类号： H01L21/768

CPC分类号： H01L21/76829 ,  C23C16/325 ,  C30B25/105 ,  C30B29/36 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/0276 ,  H01L21/0445 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  Y10S438/932 ,  Y10S438/952 ,  H01L2924/00

摘要： The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).

摘要翻译： 本发明提供了在IC应用中，根据某些工艺方案形成的SiC材料，其可用作包括前金属电介质（PMD）水平在内的多层次的阻挡层，蚀刻停止层和/或ARC，并且提供 原位沉积有用于阻挡层的SiC材料的介电层，以及蚀刻停止层和ARC。 本发明还可以利用含有诸如氨的还原剂的等离子体来减少可能发生的任何氧化物，特别是在诸如铜填充特征的金属表面上。 这种特殊的SiC材料可用于复杂的结构，例如镶嵌结构，并且有利于原位沉积，特别是当用于不同层的多个容量时，例如阻挡层，蚀刻停止层和ARC，并且可以包括 相关电介质层的原位沉积。

公开(公告)号：US07482245B1

公开(公告)日：2009-01-27

申请号：US11471958

申请日：2006-06-20

申请人： Jengyi Yu ,  Chi-I Lang ,  Judy H. Huang

发明人： Jengyi Yu ,  Chi-I Lang ,  Judy H. Huang

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7846

摘要： High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.

摘要翻译： 高密度等离子体（HDP）技术形成具有顺序调制应力分布的氧化硅膜。 HDP技术使用足够低的温度以在晶体管架构和制造工艺中沉积氧化硅膜，其有效地用于产生通道应变而不会不利地影响晶体管的完整性。 方法涉及使用高密度等离子体化学气相沉积工艺在一部分沉积的电介质上部分填充衬底上的沟槽。 该过程的条件被配置为在沉积的电介质的第一部分中产生第一应力状态。 然后可以修改沉积工艺条件以在沉积的电介质中产生不同的应力条件。 可以使用改进的沉积工艺进一步填充部分填充的沟槽，以产生额外的电介质并且可以重复直到填充沟槽。 晶体管应变可以在使用STI间隙填充中的应力分布调制的NMOS或PMOS器件中产生。

公开(公告)号：US07211525B1

公开(公告)日：2007-05-01

申请号：US11082369

申请日：2005-03-16

申请人： Sunil Shanker ,  Sean Cox ,  Chi-I Lang ,  Judy H. Huang ,  Minh Anh Nguyen ,  Ken Vo ,  Wenxian Zhu

发明人： Sunil Shanker ,  Sean Cox ,  Chi-I Lang ,  Judy H. Huang ,  Minh Anh Nguyen ,  Ken Vo ,  Wenxian Zhu

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/31612 ,  C23C16/0245 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/76224 ,  H01L21/76837

摘要： Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.

摘要翻译： 描述了用绝缘膜填充半导体衬底上的间隙的方法。 该方法减少或消除侧壁沉积和顶帽形成。 在电介质膜沉积期间，这些方法还减少或消除了蚀刻步骤的需要。 所述方法包括在沉积介质膜之前用氢等离子体处理半导体衬底。 在一些实施方案中，使用氢处理与高速沉积工艺相结合。

公开(公告)号：US07070657B1

公开(公告)日：2006-07-04

申请号：US09418818

申请日：1999-10-15

申请人： David Cheung ,  Joe Feng ,  Judy H. Huang ,  Wai-Fan Yau

发明人： David Cheung ,  Joe Feng ,  Judy H. Huang ,  Wai-Fan Yau

IPC分类号： C23C16/52 ,  C23F1/00 ,  H01L21/306

CPC分类号： G03F7/091

摘要： This invention provides a stable process for depositing an antireflective layer. Helium gas is used to lower the deposition rate of plasma-enhanced silane oxide, silane oxynitride, and silane nitride processes. Helium is also used to stabilize the process, so that different films can be deposited. The invention also provides conditions under which process parameters can be controlled to produce antireflective layers with varying optimum refractive index, absorptive index, and thickness for obtaining the desired optical behavior.

摘要翻译： 本发明提供一种用于沉积抗反射层的稳定方法。 氦气用于降低等离子体增强硅烷氧化物，硅氮氧化物和氮化硅工艺的沉积速率。 氦也用于稳定工艺，使得可以沉积不同的膜。 本发明还提供了可以控制工艺参数以产生具有变化的最佳折射率，吸收指数和厚度以获得所需光学行为的抗反射层的条件。

公开(公告)号：US06858153B2

公开(公告)日：2005-02-22

申请号：US10011368

申请日：2001-11-05

申请人： Claes H. Bjorkman ,  Min Melissa Yu ,  Hongquing Shan ,  David W. Cheung ,  Wai-Fan Yau ,  Kuowei Liu ,  Nasreen Gazala Chapra ,  Gerald Yin ,  Farhad K. Moghadam ,  Judy H. Huang ,  Dennis Yost ,  Betty Tang ,  Yunsang Kim

发明人： Claes H. Bjorkman ,  Min Melissa Yu ,  Hongquing Shan ,  David W. Cheung ,  Wai-Fan Yau ,  Kuowei Liu ,  Nasreen Gazala Chapra ,  Gerald Yin ,  Farhad K. Moghadam ,  Judy H. Huang ,  Dennis Yost ,  Betty Tang ,  Yunsang Kim

IPC分类号： H01L21/302 ,  A01C15/02 ,  A01C17/00 ,  C23C16/40 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  C23F1/00

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

摘要翻译： 沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。 电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。 具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。 用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

公开(公告)号：US06209484B1

公开(公告)日：2001-04-03

申请号：US09551021

申请日：2000-04-17

申请人： Judy H. Huang ,  Wai-Fan Yau ,  David Cheung ,  Chan-Lon Yang

发明人： Judy H. Huang ,  Wai-Fan Yau ,  David Cheung ,  Chan-Lon Yang

IPC分类号： C23C1600

CPC分类号： C23C16/308 ,  C23C16/345 ,  C23C16/52 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829

摘要： A method and apparatus for depositing an etch stop layer. The method begins by introducing process gases into a processing chamber in which a substrate is disposed. An etch stop layer is then deposited over the substrate. An overlying layer is then deposited over the etch stop layer. The etch stop layer substantially protects underlying materials from the etchants used in patterning the overlying layer. Moreover, the etch stop layer also possesses advantageous optical characteristics, making it suitable for use as an antireflective coating in the patterning of layers underlying the etch stop layer.

摘要翻译： 一种沉积蚀刻停止层的方法和装置。 该方法开始于将工艺气体引入其中设置衬底的处理室中。 然后在衬底上沉积蚀刻停止层。 然后将上覆层沉积在蚀刻停止层上。 蚀刻停止层基本上保护用于图案化上覆层的蚀刻剂的下层材料。 此外，蚀刻停止层还具有有利的光学特性，使其适合用作在蚀刻停止层下面的图案图案中的抗反射涂层。

公开(公告)号：US5908672A

公开(公告)日：1999-06-01

申请号：US950923

申请日：1997-10-15

申请人： Choon Kun Ryu ,  Judy H. Huang ,  David Cheung

发明人： Choon Kun Ryu ,  Judy H. Huang ,  David Cheung

IPC分类号： C23C16/34 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/02131 ,  C23C16/345 ,  C23C16/401 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31629 ,  Y10S438/958

摘要： A planarized passivation layer is described. A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS). The inclusion of fluorine in the process chemistry provides good gap-fill characteristics in the film thus formed. The TEFS-based process employed by the present invention employs a low deposition rate, on the order of less than about 4500 .ANG./min, and preferably above 3000 .ANG./min, when depositing the FSG layer. The use of low deposition rate results in a positively sloped profile, preventing the formation of voids during the deposition of the FSG layer and the silicon nitride layer.

摘要翻译： 描述了平坦化的钝化层。 本发明的平坦化钝化层优选包括氟硅酸盐玻璃（FSG）层和氮化硅层。 FSG层优选使用三乙氧基氟硅烷（TEFS）和原硅酸四乙酯（TEOS）沉积。 在工艺化学中包含氟在由此形成的膜中提供良好的间隙填充特性。 当沉积FSG层时，本发明采用的基于TEFS的方法使用低沉积速率，小于约4500安培/分钟，优选高于3000安培/分钟。 使用低沉积速率导致正倾斜的轮廓，防止在沉积FSG层和氮化硅层期间形成空隙。

公开(公告)号：US07888233B1

公开(公告)日：2011-02-15

申请号：US12411243

申请日：2009-03-25

申请人： Vishal Gauri ,  Raashina Humayun ,  Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

发明人： Vishal Gauri ,  Raashina Humayun ,  Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

IPC分类号： H01L21/4757

CPC分类号： H01L21/31 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/31608 ,  H01L21/76224

摘要： Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.

摘要翻译： 本发明的方法涉及通过在间隙中形成可流动的膜来填充具有固体电介质材料的衬底上的间隙。 可流动膜提供一致的，无空隙的间隙填充。 然后将膜转化成固体电介质材料。 以这种方式，用固体电介质材料填充衬底上的间隙。 根据各种实施方案，所述方法包括使电介质前体与氧化剂反应以形成电介质材料。 在某些实施方案中，电介质前体冷凝并随后与氧化剂反应以形成电介质材料。 在某些实施方案中，气相反应物反应形成冷凝的可流动的膜。