公开(公告)号：US20130320516A1

公开(公告)日：2013-12-05

申请号：US13572833

申请日：2012-08-13

申请人： Doo Hwan Lee ,  Tae Sung Jeong ,  Yul Kyo Chung

发明人： Doo Hwan Lee ,  Tae Sung Jeong ,  Yul Kyo Chung

IPC分类号： H01L21/52 ,  H01L21/54 ,  H01L23/24 ,  H01L21/60 ,  H01L23/498 ,  H01L23/055

CPC分类号： H01L21/52 ,  H01L21/54 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

摘要翻译： 这里公开了一种半导体封装及其制造方法，所述半导体封装包括：模制构件，其中形成有空腔; 安装在腔体中的装置; 绝缘构件，其形成在所述空腔内并且在所述模制构件和所述装置之上和/或之下; 形成在所述绝缘构件上的电路层，并且包括与所述装置电连接的通孔和连接垫; 形成在电路层上的阻焊层，并且具有暴露连接焊盘的上部的开口; 以及形成在开口中的焊球。

公开(公告)号：US20120061833A1

公开(公告)日：2012-03-15

申请号：US12972310

申请日：2010-12-17

申请人： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

发明人： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83001 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

摘要翻译： 本文公开了嵌入式球栅阵列基板及其制造方法。 嵌入式球栅阵列包括：其中具有空腔的芯层; 嵌入在芯层的空腔中的半导体器件; 第一电路层，具有包括在其上形成的引线接合焊盘的电路图案; 第二电路层，其具有包括形成在其上的焊球图案的电路图案; 以及将半导体器件电连接到引线接合焊盘的线。

公开(公告)号：US08102043B2

公开(公告)日：2012-01-24

申请号：US13006278

申请日：2011-01-13

申请人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

发明人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

IPC分类号： H01L25/07 ,  H01L21/98

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.

摘要翻译： 一种堆叠集成电路和封装系统的制造方法，包括：在顶部基板上安装耐高温层; 将第一顶部集成电路安装在耐高温层上; 在第一顶部集成电路上安装第二顶部集成电路; 在第一顶部集成电路，第二顶部集成电路和顶部衬底上模制密封剂; 在与第二顶部集成电路相对的表面上在第一顶部集成电路上安装第三顶部集成电路; 在第三顶部集成电路上安装第四顶部集成电路; 在第三顶部集成电路，第四顶部集成电路和顶部衬底上成型密封剂; 在顶部基板的下表面上形成顶部电连接器; 并将底部封装安装到顶部电连接器。

公开(公告)号：US08067831B2

公开(公告)日：2011-11-29

申请号：US11162629

申请日：2005-09-16

申请人： Hyeog Chan Kwon ,  Tae Sung Jeong ,  Jae Han Chung ,  Taeg Ki Lim ,  Jong Wook Ju

发明人： Hyeog Chan Kwon ,  Tae Sung Jeong ,  Jae Han Chung ,  Taeg Ki Lim ,  Jong Wook Ju

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/24 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16238 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2224/83 ,  H01L2224/82

摘要： An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.

摘要翻译： 提供一种集成电路封装系统，包括形成第一基板，将第一集成电路安装到第一基板，以及形成与第一集成电路接触的第一平面互连并将第一集成电路电连接到第一基板。

公开(公告)号：US20110108976A1

公开(公告)日：2011-05-12

申请号：US13006278

申请日：2011-01-13

申请人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

发明人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

IPC分类号： H01L25/07 ,  H01L21/98

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.

摘要翻译： 一种堆叠集成电路和封装系统的制造方法，包括：在顶部基板上安装耐高温层; 将第一顶部集成电路安装在耐高温层上; 在第一顶部集成电路上安装第二顶部集成电路; 在第一顶部集成电路，第二顶部集成电路和顶部衬底上模制密封剂; 在与第二顶部集成电路相对的表面上在第一顶部集成电路上安装第三顶部集成电路; 在第三顶部集成电路上安装第四顶部集成电路; 在第三顶部集成电路，第四顶部集成电路和顶部衬底上成型密封剂; 在顶部基板的下表面上形成顶部电连接器; 并将底部封装安装到顶部电连接器。

公开(公告)号：US20110083891A1

公开(公告)日：2011-04-14

申请号：US12631555

申请日：2009-12-04

申请人： Hong Bok WE ,  Tae Sung JEONG ,  Dae Jun KIM

发明人： Hong Bok WE ,  Tae Sung JEONG ,  Dae Jun KIM

IPC分类号： H05K1/18 ,  B29C65/00 ,  B23K31/02

CPC分类号： H01L23/5389 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K1/186 ,  H05K1/189 ,  H05K3/4602 ,  H05K2201/0394 ,  H05K2201/096 ,  H05K2201/10674

摘要： Disclosed herein is an electronic component-embedded printed circuit board, including: a flexible film; an insulation layer formed on one side of the flexible film; an electronic component mounted on the one side of the flexible film in a face-down manner such that the electronic component is buried in the insulation layer; and a circuit layer including a connecting pattern which is formed on the one side of the flexible film and is connected with a connecting terminal of the electronic component by a connecting member. The electronic component-embedded printed circuit board is advantageous in that the position alignment between the connecting patterns and the connecting terminals is easy and the connection reliability therebetween is high because the connecting patterns formed on a flexible film are directly connected to the connecting terminals of an electronic component using connecting members, and in that the production cost thereof can be reduced because additional rewiring is not required.

摘要翻译： 这里公开了一种电子部件嵌入式印刷电路板，包括：柔性膜; 形成在柔性膜的一侧上的绝缘层; 以面向下方式安装在柔性膜的一侧上的电子部件，使得电子部件埋设在绝缘层中; 以及电路层，其包括形成在柔性膜的一侧上的连接图案，并且通过连接构件与电子部件的连接端子连接。 电子元件嵌入式印刷电路板的优点在于，连接图案和连接端子之间的位置对准容易，并且其间的连接可靠性高，因为形成在柔性膜上的连接图案直接连接到柔性膜的连接端子 使用连接构件的电子部件，并且由于不需要额外的重新布线，可以减少其生产成本。

公开(公告)号：US07875966B2

公开(公告)日：2011-01-25

申请号：US11255740

申请日：2005-10-21

申请人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

发明人： Tae Sung Jeong ,  Hyeog Chan Kwon ,  Youngcheol Kim

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.

摘要翻译： 一种堆叠集成电路和封装系统，包括在顶部衬底的上表面上附接第一顶部集成电路，将第二顶部集成电路附接在顶部衬底的下表面上，在顶部衬底的下表面上形成顶部电连接器 ，并将底部封装连接到顶部电连接器。

公开(公告)号：US20100142170A1

公开(公告)日：2010-06-10

申请号：US12320492

申请日：2009-01-27

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H05K3/426 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种芯片嵌入式印刷电路板及其制造方法，其特征在于，提供一种芯片嵌入式印刷电路板，其具备：具有通孔形成的绝缘层; 嵌入绝缘层中的第一芯片和第二芯片，并且在其一个表面上分别暴露于绝缘层的上表面和下表面的焊盘; 形成在绝缘层的上表面上以连接到第一芯片的焊盘和通孔的上部图案; 以及形成在绝缘层的下表面上以连接到第二芯片的焊盘和通孔的下图案。 另外，本发明提供一种嵌入式芯片的印刷电路板的制造方法。

公开(公告)号：US20100134991A1

公开(公告)日：2010-06-03

申请号：US12320523

申请日：2009-01-28

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The prevent invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种嵌入式芯片的印刷电路板及其制造方法。 本发明提供了一种芯片嵌入式印刷电路板，其包括：绝缘层，其嵌入在上部设置有柱的芯片，通过绝缘层形成的通孔，形成在要连接到柱的绝缘层的上部的上部图案;以及 形成在绝缘层的与通孔连接的下部的通孔和下部图案及其制造方法。

公开(公告)号：US20100084754A1

公开(公告)日：2010-04-08

申请号：US12591792

申请日：2009-12-01

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

IPC分类号： H01L25/065

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate.

摘要翻译： 一种半导体封装，其包括在其上形成有预先设计的图案的第一基板; 通过倒装芯片方法在所述第一基板的一侧上安装的第一芯片; 在所述第一基板的边缘上形成为预定厚度的支撑件; 插入器，其具有放置在支撑体上的边缘，使得所述插入件覆盖所述第一基板并在所述插入件与所述第一基板之间形成空腔，并且具有分别形成在其两侧的预先设计的图案; 穿过支撑件和插入件的通孔; 第二芯片，安装在所述插入器的面向所述第一基板的一侧上; 放置在所述插入件的另一侧上的第二衬底，其中至少一个导电球定位在其间; 以及安装在所述第二基板上的第三芯片。