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公开(公告)号：US20210143448A1
公开(公告)日：2021-05-13
申请号：US16680701
申请日：2019-11-12
申请人： Bryan M. BLACKBURN , Lei WANG , Thomas A. LANGDO
发明人： Bryan M. BLACKBURN , Lei WANG , Thomas A. LANGDO
IPC分类号： H01M8/0245 , H01M8/0232 , H01M8/0282 , H01M8/0236 , H01M8/2432
摘要： In various embodiments, components such as interconnects and/or endplates of a solid-state electrochemical device are coated with materials such as, for example, graphite, copper, aluminum, carbide ceramics, nitride ceramics, conversion coatings, or aluminum intermetallics.
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2.发明授权Devices, systems, and methods for controlling the temperature of resonant elements 有权用于控制谐振元件温度的器件，系统和方法公开(公告)号：US08653897B2
公开(公告)日：2014-02-18
申请号：US13567915
申请日：2012-08-06
CPC分类号： H03L1/04 , H01L35/325
摘要： A thermoelectric device transfers heat away from or toward an object using the Peltier effect. In some embodiments, the length of at least one thermoelectric element is at least ten times greater than a combined average cross-sectional dimension, orthogonal to the length, of two thermoelectric elements.
摘要翻译： 热电装置使用珀耳帖效应将热量从物体或朝向物体传递。 在一些实施例中，至少一个热电元件的长度是与两个热电元件的长度正交的组合平均截面尺寸的至少十倍。
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3.发明申请Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication 有权晶格不匹配的半导体结构具有减少的位错缺陷密度和相关的器件制造方法公开(公告)号：US20110049568A1
公开(公告)日：2011-03-03
申请号：US12845593
申请日：2010-07-28
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/02609 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02612 , H01L21/02639 , H01L21/02647 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/0605 , H01L27/092 , H01L29/04 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/66666 , H01L29/66795 , H01L29/778 , H01L29/78 , H01L29/7827 , H01L29/7835 , H01L29/7848 , H01L29/785 , H01L29/78687 , H01L31/028 , H01L31/0304 , H01L31/036 , H01L31/1808 , H01L33/20 , H01L33/30 , H01L33/34 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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公开(公告)号：US20100206216A1
公开(公告)日：2010-08-19
申请号：US12711560
申请日：2010-02-24
申请人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
发明人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
IPC分类号： C30B25/00
CPC分类号： C30B29/52 , C23C16/029 , C23C16/22 , C23C16/4401 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
摘要翻译： 在半导体材料上沉积梯度Si 1-x Ge x层的过程中使颗粒产生最小化的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体具有分解 温度大于锗烷，并沉积具有大于约0.15的最终Ge含量并且小于约0.3颗粒/ cm 2的颗粒密度的梯度Si 1-x Ge 2层在衬底上 。
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5.发明授权Methods of fabricating semiconductor structures having epitaxially grown source and drain elements 有权制造具有外延生长的源极和漏极元件的半导体结构的方法公开(公告)号：US07439164B2
公开(公告)日：2008-10-21
申请号：US11489787
申请日：2006-07-20
CPC分类号： H01L29/66628 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28562 , H01L29/1054 , H01L29/456 , H01L29/51 , H01L29/665 , H01L29/6656 , H01L29/7834
摘要： Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
摘要翻译： 本文公开了使用市售化学气相沉积系统制造无面半导体结构的方法。 本发明的关键方面包括在半导体衬底上选择性地沉积至少一种半导体材料的外延层，同时原位掺杂外延层以抑制刻面形成。 通过以预定水平原位掺杂外延层而不是通过操纵间隔物组成和几何形状来抑制选择性外延生长期间的面板减轻了对器件设计的严格要求，并且增加了间隔物制造过程中对变异性的公差。
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6.发明申请Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication 审中-公开具有减少的位错缺陷密度的晶格不匹配的半导体结构和用于器件制造的相关方法公开(公告)号：US20070267722A1
公开(公告)日：2007-11-22
申请号：US11436062
申请日：2006-05-17
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/66666 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/785 , H01L29/78687 , H01L31/1808 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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公开(公告)号：US08535984B2
公开(公告)日：2013-09-17
申请号：US13222764
申请日：2011-08-31
IPC分类号： H01L21/00
CPC分类号： H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/31 , H01L23/3157 , H01L23/5384 , H01L23/5389 , H01L23/544 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68359 , H01L2221/68377 , H01L2223/54426 , H01L2223/54473 , H01L2224/04105 , H01L2224/24227 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.
摘要翻译： 电子模块通过将微电子管芯封装在衬底中的空腔内而形成。
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公开(公告)号：US08273603B2
公开(公告)日：2012-09-25
申请号：US12407252
申请日：2009-03-19
CPC分类号： H01L21/486 , B81B2207/012 , B81C1/00333 , B81C2201/019 , B81C2201/0191 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68359 , H01L2221/68377 , H01L2224/04105 , H01L2224/24227 , H01L2224/73267 , H01L2224/8203 , H01L2224/92144 , H01L2224/9222 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01084 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15151 , H01L2924/15153 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/49124 , H01L2924/00
摘要： In accordance with a method for forming an interposer, a fill hole is formed in a first side of a substrate and a cavity is formed in a second side. The cavity is in fluidic communication with the fill hole. A plurality of posts is formed in the cavity, and an encapsulant is injected through the fill hole into the cavity to encapsulate the plurality of posts. In accordance with a method of thermal management, an electronic component and a heat sink are disposed on opposing sides of an interposer that includes a plurality of encapsulated posts.
摘要翻译： 根据用于形成插入件的方法，在基板的第一侧中形成填充孔，并且在第二侧形成空腔。 空腔与填充孔流体连通。 在空腔中形成多个柱，并且通过填充孔将密封剂注入空腔中以封装多个柱。 根据热管理的方法，电子部件和散热器布置在包括多个密封柱的插入件的相对侧上。
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9.发明授权Devices, systems, and methods for controlling the temperature of resonant elements 有权用于控制谐振元件温度的器件，系统和方法公开(公告)号：US08248173B2
公开(公告)日：2012-08-21
申请号：US12768501
申请日：2010-04-27
CPC分类号： H03L1/04 , H01L35/325
摘要： A thermoelectric device transfers heat away from or toward an object using the Peltier effect. In some embodiments, the length of at least one thermoelectric element is at least ten times greater than a combined average cross-sectional dimension, orthogonal to the length, of two thermoelectric elements.
摘要翻译： 热电装置使用珀耳帖效应将热量从物体或朝向物体传递。 在一些实施例中，至少一个热电元件的长度是与两个热电元件的长度正交的组合平均截面尺寸的至少十倍。
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公开(公告)号：US08187379B2
公开(公告)日：2012-05-29
申请号：US13074777
申请日：2011-03-29
申请人： Eugene Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
发明人： Eugene Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
IPC分类号： C30B21/02
CPC分类号： C30B29/52 , C23C16/029 , C23C16/22 , C23C16/4401 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
摘要翻译： 在半导体材料上沉积梯度Si1-xGex层期间最小化颗粒产生的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体的分解温度大于锗烷，并沉积 分级的Si1-xGex层，其具有大于约0.15的最终Ge含量和小于约0.3颗粒/ cm 2的颗粒密度。
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