公开(公告)号：US07015064B1

公开(公告)日：2006-03-21

申请号：US10830818

申请日：2004-04-23

申请人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar

发明人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/67282 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Wafer level techniques for marking the back surfaces of integrated circuit devices are described. A wafer mounting tape is provided that includes releasable pigments. The pigments can be released by exposing the mounting tape to a selected frequency of electromagnetic radiation (e.g., UV light). The released pigments mark the back surface of the wafer. The exposure and pigmentation may be controlled using a variety of techniques including servo control of a light source, the use of masks or reticles or other suitable techniques. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.

摘要翻译： 描述了用于标记集成电路器件的背面的晶片级技术。 提供了包括可释放颜料的晶片安装带。 可以通过将安装带暴露于选定频率的电磁辐射（例如，UV光）来释放颜料。 释放的颜料标记晶片的背面。 可以使用包括光源的伺服控制，掩模或掩模版的使用或​​其它合适技术的各种技术来控制曝光和色素沉着。 标记可以在包括聚合物背涂层，金属化膜或直接在半导体材料上的任何合适的背面材料上进行。

公开(公告)号：US07642175B1

公开(公告)日：2010-01-05

申请号：US11542817

申请日：2006-10-03

申请人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

发明人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L21/46

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/552 ,  H01L24/27 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2223/5448 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.

摘要翻译： 描述了在集成电路器件的背面上形成保护涂层的晶片级方法。 一方面，将具有背涂层和安装层的带施加到晶片的背面。 背涂层被固化或设置成使得背涂层固定到晶片的背面。 此后，除去背涂层/安装带的安装层，同时留下附着在集成电路器件背面的背涂层。 在一些实施例中，安装层包括当暴露于UV光时释放的紫外线（UV）敏感的粘合剂材料。 所描述的布置可以用于形成具有非常薄的保护性底涂层的集成电路。 作为示例，可以容易地获得厚度在5至50微米范围内的不透明保护膜。

公开(公告)号：US06972244B1

公开(公告)日：2005-12-06

申请号：US10831390

申请日：2004-04-23

申请人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar ,  You Chye How ,  Tian Oon Goh ,  Soi Chong Low

发明人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar ,  You Chye How ,  Tian Oon Goh ,  Soi Chong Low

IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/68 ,  H01L21/78 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.

摘要翻译： 描述了用于标记集成电路器件的背面的晶片级技术。 在由安装带支撑的同时激光标记晶片的背面。 在一些实施例中，安装带足够透明，使得激光穿过安装带并标记晶片的背面。 在其它实施例中，在标记过程中，激光器实际上可燃烧安装带（或其部分）。 标记可以在包括聚合物背涂层，金属化膜或直接在半导体材料上的任何合适的背面材料上进行。

公开(公告)号：US07135385B1

公开(公告)日：2006-11-14

申请号：US10830820

申请日：2004-04-23

申请人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

发明人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L21/46

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/552 ,  H01L24/27 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2223/5448 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.

摘要翻译： 描述了在集成电路器件的背面上形成保护涂层的晶片级方法。 一方面，将具有背涂层和安装层的带施加到晶片的背面。 背涂层被固化或设置成使得背涂层固定到晶片的背面。 此后，除去背涂层/安装带的安装层，同时留下附着在集成电路器件背面的背涂层。 在一些实施例中，安装层包括当暴露于UV光时释放的紫外线（UV）敏感的粘合剂材料。 所描述的布置可以用于形成具有非常薄的保护性底涂层的集成电路。 作为示例，可以容易地获得厚度在5至50微米范围内的不透明保护膜。

公开(公告)号：US08951847B2

公开(公告)日：2015-02-10

申请号：US13611754

申请日：2012-09-12

申请人： Nikhil Vishwanath Kelkar ,  Kai Liu

发明人： Nikhil Vishwanath Kelkar ,  Kai Liu

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48141 ,  H01L2224/48145 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

摘要翻译： 用于器件封装的引线框的实施例不仅用于对外部世界的I / O引脚的结构支持和连接，还用于引导框架上方和下方的外壳和/或安装设备。 导电框架还用作一个器件上的焊盘之间的低电阻互连和良好的电流载体，或者位于引线框架上方和/或下方的不同器件上的焊盘之间。

公开(公告)号：US06900110B1

公开(公告)日：2005-05-31

申请号：US10318426

申请日：2002-12-13

申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L21/76

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013

摘要： A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

摘要翻译： 描述了一种晶片级制造的芯片级集成电​​路封装，其具有形成在封装的集成电路管芯之间的空气间隙和位于管芯上并导电地附接于管芯的柔性引线。 柔性引线上的接触凸块偏移可提供集成电路封装与其他基板的连接。 在一些实施例中，柔性引线包括覆盖有外部弹性层的导电层，并且还可以包括导电层下面的内部弹性层。 外部弹性层具有通过其形成的通孔，其暴露下面的导电层。 通孔沿柔性引线偏离与接合焊盘的水平距离，其中顺应引线与导电耦合。 芯片尺寸封装提供了管芯与管芯所连接的任何衬底之间高度兼容的连接。

公开(公告)号：US06398034B1

公开(公告)日：2002-06-04

申请号：US09515588

申请日：2000-02-29

申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

IPC分类号： B65D8500

CPC分类号： B65D73/02 ,  H05K13/0084

摘要： The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip's electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by “snap-fitting” each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the “snap-fitting” of electrical contacts into receptacle holes.

摘要翻译： 本发明提供了一种设计用于在运输期间存储芯片的低成本载带。 本发明包括载带，该载带包含设计成通过扣紧芯片的电触点将芯片固定到载带上的插座孔。 插座孔防止芯片旋转和物理移动。 插座孔以图案形成以匹配倒装芯片族的标准化电接触图案。 容纳孔的直径的尺寸可以略小于电触头的直径，使得芯片通过将每个电触头“卡扣配合”到插座孔中来固定。 可以在容纳孔的边缘上形成浮雕狭缝，以便于将电触点“卡扣配合”到插孔中。

公开(公告)号：US06249044B1

公开(公告)日：2001-06-19

申请号：US09335440

申请日：1999-06-17

申请人： Pai-Hsiang Kao ,  Nikhil Vishwanath Kelkar

发明人： Pai-Hsiang Kao ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L2900

CPC分类号： H01L23/552 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/16 ,  H01L2924/01322 ,  H01L2924/3025

摘要： A light shield is provided for light sensitive flip chip integrated circuits. The flip chip includes an under bump layer to portions of which solder bumps are attached. A separate portion of this under bump layer is used to provide the light shield. The light shield excludes ambient light from the most light sensitive portions of the circuit so that the electrical characteristics of the flip chip integrated circuit are not significantly altered when the flip chip is operated in ambient light.

摘要翻译： 为光敏倒装芯片集成电路提供了一个遮光罩。 倒装芯片包括底部凸起层，其中部分焊料凸点被附着。 该凹凸层的单独部分用于提供遮光罩。 遮光罩不包括来自电路的最光敏部分的环境光，因此当倒装芯片在环境光中工作时，倒装芯片集成电路的电气特性不会明显改变。

公开(公告)号：US07241643B1

公开(公告)日：2007-07-10

申请号：US11126461

申请日：2005-05-10

申请人： Nikhil Vishwanath Kelkar ,  Hem P. Takiar

发明人： Nikhil Vishwanath Kelkar ,  Hem P. Takiar

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05099

摘要： A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit film further includes routing conductors that connect inner landings on the bottom surface of the flexible circuit film with outer landings on the top surface of the flexible circuit film. The outer landings are offset a horizontal distance from the inner landings. In some embodiments, contact bumps are formed on the outer landings of the flexible circuit film layer for use in connecting the package to other substrates. The wafer level chip scale package provides a highly compliant connection between the die and any other substrate that the die is attached to.

摘要翻译： 描述了一种晶片级制造的集成电路封装，其具有形成在封装的集成电路管芯之间的空气间隙和柔性电路膜，所述柔性电路膜位于通过形成在管芯上的升高的互连件并且导电地附接到管芯上。 柔性电路膜还包括将柔性电路膜的底表面上的内部平台与柔性电路膜的顶表面上的外部平台连接的布线导体。 外部着陆偏离内部平台的水平距离。 在一些实施例中，接触凸块形成在柔性电路膜层的外部平台上，用于将封装连接到其它基板。 晶片级芯片级封装提供了管芯与管芯所连接的任何其它衬底之间高度兼容的连接。

公开(公告)号：US06462426B1

公开(公告)日：2002-10-08

申请号：US09738122

申请日：2000-12-14

申请人： Nikhil Vishwanath Kelkar ,  Stephen A. Gee

发明人： Nikhil Vishwanath Kelkar ,  Stephen A. Gee

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit device comprising a semiconductor die having a plurality of conductive pads. Over the conductive pads is formed a passivation layer that has a plurality of passivation layer openings. The passivation layer openings are positioned over an associated one of the conductive pads. Barrier base pads are placed in electrical contact with the conductive pads such that a portion of each of barrier base pads cover at least the perimeter of each passivation layer opening. Each of the barrier base pads prevents cracks from propagating through the integrated circuit device. In another aspect of the invention, the integrated circuit device is attached to an external substrate by connecting the contact bumps to the bond pads on an electronic substrate. In yet another aspect of the invention, a method for manufacturing the integrated circuit device is described.

摘要翻译： 一种集成电路器件，包括具有多个导电焊盘的半导体管芯。 在导电焊盘上形成钝化层，该钝化层具有多个钝化层开口。 钝化层开口位于相关联的导电焊盘之上。 阻挡基垫被放置成与导电垫电接触，使得每个阻挡基底垫的一部分至少覆盖每个钝化层开口的周边。 每个阻挡基座防止裂纹通过集成电路器件传播。 在本发明的另一方面，通过将接触凸块连接到电子基板上的接合焊盘，将集成电路器件附接到外部基板。 在本发明的另一方面，描述了一种用于制造集成电路器件的方法。