公开(公告)号：US20200295041A1

公开(公告)日：2020-09-17

申请号：US16887433

申请日：2020-05-29

Applicant: Applied Materials, Inc.

Inventor： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US20170207088A1

公开(公告)日：2017-07-20

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20170178956A1

公开(公告)日：2017-06-22

申请号：US15384219

申请日：2016-12-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Jin Hee PARK ,  Tae Hong HA ,  Sang-Hyeob LEE ,  Thomas Jongwan KWON ,  Jaesoo AHN ,  Xianmin TANG ,  Er-Xuan PING ,  Sree KESAPRAGADA

IPC: H01L21/768 ,  C23C16/458 ,  C23C16/48 ,  C23C16/455 ,  H01L21/285 ,  H01L21/67

CPC classification number: H01L21/76879 ,  C23C16/045 ,  C23C16/16 ,  C23C16/18 ,  C23C16/45512 ,  C23C16/45561 ,  C23C16/481 ,  C23C16/56 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

公开(公告)号：US20160372371A1

公开(公告)日：2016-12-22

申请号：US15189768

申请日：2016-06-22

Applicant: Applied Materials, Inc.

Inventor： Kaushal K. SINGH ,  Er-Xuan PING ,  Xianmin TANG ,  Sundar RAMAMURTHY ,  Randhir THAKUR

IPC: H01L21/768

CPC classification number: H01L21/28518 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53219

Abstract: Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.

Abstract translation: 本文所述的实施方案一般涉及形成硅化物材料的方法。 根据本文所述的实施方案形成的硅化物材料可以用作接触和/或互连结构，并且可以提供优于常规硅化物形成方法的优点。 在一个实施例中，一个或多个过渡金属和铝层可以沉积在含硅衬底上，并且过渡金属层可以沉积在一个或多个过渡金属和铝层上。 可以进行退火工艺以形成金属硅化物材料。

公开(公告)号：US20190115365A1

公开(公告)日：2019-04-18

申请号：US16151467

申请日：2018-10-04

Applicant: Applied Materials, Inc.

Inventor： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US20160372351A1

公开(公告)日：2016-12-22

申请号：US15188103

申请日：2016-06-21

Applicant: Applied Materials, Inc.

Inventor： Kaushal K. SINGH ,  Deepak JADHAV ,  Ashutosh AGARWAL ,  Ashish GOEL ,  Vijay PARIHAR ,  Er-Xuan PING ,  Randhir P.S. THAKUR

IPC: H01L21/67 ,  C23C16/455 ,  H01L21/475 ,  H01L21/441 ,  H01L21/02 ,  H01L21/4757

CPC classification number: C23C16/45525 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02381 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/6723

Abstract: Embodiments described herein provide a remote plasma system utilizing a microwave source. Additionally, generation and deposition techniques for 2D transition metal chalcogenides with large area uniformity utilizing microwave assisted generation of radicals is disclosed. Plasma may be generated remotely utilizing the microwave source. A processing platform configured to deposit 2D transition metal chalcogenides is also disclosed.

Abstract translation: 本文所述的实施例提供了利用微波源的远程等离子体系统。 另外，公开了利用微波辅助生成自由基的具有大面积均匀性的二维过渡金属硫族化物的生成和沉积技术。 可以使用微波源远程产生等离子体。 还公开了一种配置成沉积2D过渡金属硫属化物的处理平台。

公开(公告)号：US20160372330A1

公开(公告)日：2016-12-22

申请号：US14745367

申请日：2015-06-19

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Kai MA ,  Thomas KWON ,  Kaushal K. SINGH ,  Er-Xuan PING

IPC: H01L21/285 ,  C23C16/06 ,  H01L23/532 ,  C23C28/00 ,  H01L21/768 ,  C23C14/06 ,  C23C14/16

CPC classification number: H01L23/53266 ,  C23C14/0641 ,  C23C16/401 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  H01L21/76838

Abstract: The present disclosure provides a film stack structure formed on a substrate and methods for forming the film stack structure on the substrate. In one embodiment, the method for forming a film stack structure on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate and depositing a metal layer on the first adhesion layer, wherein the first adhesion layer and the metal layer form a stress neutral structure.

Abstract translation: 本公开提供了一种形成在基板上的薄膜叠层结构以及在该基板上形成薄膜叠层结构的方法。 在一个实施例中，用于在衬底上形成膜堆叠结构的方法包括在形成在衬底上的氧化物层上沉积第一粘附层并在第一粘合层上沉积金属层，其中第一粘附层和金属层形成 应力中性结构。

公开(公告)号：US20230207638A1

公开(公告)日：2023-06-29

申请号：US17562938

申请日：2021-12-27

Applicant: Applied Materials, Inc.

Inventor： Yi ZHENG ,  Er-Xuan PING

IPC: H01L29/40 ,  H01L29/16 ,  H01L29/423 ,  H01L21/04

CPC classification number: H01L29/401 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/4236

Abstract: A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800° C., forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.

公开(公告)号：US20180277370A1

公开(公告)日：2018-09-27

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/02 ,  H01L49/02 ,  H01L21/311 ,  H01L27/11582

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20180233359A1

公开(公告)日：2018-08-16

申请号：US15881405

申请日：2018-01-26

Applicant: Applied Materials, Inc.

Inventor： Sungwon JUN ,  Saurabh CHOPRA ,  Thomas Jongwan KWON ,  Er-Xuan PING

IPC: H01L21/02 ,  C23C16/06

Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560° C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.