公开(公告)号：US5610426A

公开(公告)日：1997-03-11

申请号：US505819

申请日：1995-07-21

申请人： Akiyoshi Asai ,  Kazuhiro Tsuruta ,  Takeshi Enya

发明人： Akiyoshi Asai ,  Kazuhiro Tsuruta ,  Takeshi Enya

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L27/0266 ,  H01L27/0251 ,  H01L2924/0002

摘要： A protective circuit that can maintain effectiveness when excess voltages of both polarities are applied is placed between the input terminal of an internal CMOS inverter and an input pad. The protective circuit includes a protective resistor, a P-channel MOSFET and an N-channel MOSFET. The N-channel MOSFET is placed between a connecting line and a ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET is placed between the connecting line and the ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET releases excess negative voltage from the outside using ON-state current and the N-channel MOSFET releases excess positive voltage from the outside using ON-state current.

摘要翻译： 在内部CMOS反相器的输入端子和输入焊盘之间放置一个保护电路，该保护电路可以在施加两极性过剩电压时保持有效性。 保护电路包括保护电阻，P沟道MOSFET和N沟道MOSFET。 N沟道MOSFET放置在连接线和接地端子之间，MOSFET的栅极端子连接到连接线。 P沟道MOSFET放置在连接线和接地端子之间，MOSFET的栅极端子连接到连接线。 P沟道MOSFET使用导通状态电流从外部释放过多的负电压，N沟道MOSFET使用导通状态电流从外部释放过多的正电压。

公开(公告)号：US06191007B1

公开(公告)日：2001-02-20

申请号：US09066971

申请日：1998-04-28

申请人： Masaki Matsui ,  Shoichi Yamauchi ,  Hisayoshi Ohshima ,  Kunihiro Onoda ,  Akiyoshi Asai ,  Takanari Sasaya ,  Takeshi Enya ,  Jun Sakakibara

发明人： Masaki Matsui ,  Shoichi Yamauchi ,  Hisayoshi Ohshima ,  Kunihiro Onoda ,  Akiyoshi Asai ,  Takanari Sasaya ,  Takeshi Enya ,  Jun Sakakibara

IPC分类号： H01L21331

CPC分类号： H01L21/84 ,  H01L21/02667 ,  H01L21/2022 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  H01L2221/68363

摘要： Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.

摘要翻译： 制造半导体衬底的方法，其中半导体器件用于形成半导体器件的半导体层形成在支撑衬底上，绝缘膜介于其之间，在形成掩埋图案结构的衬底上形成半导体层是可能的 大大增加了半导体层的膜厚均匀性和膜厚可控性，特别是当半导体层被形成为极薄膜时。 结果，可以实现半导体衬底的改进的质量和特性，并且可以将这种半导体衬底部署到各种用途上。

公开(公告)号：US5663588A

公开(公告)日：1997-09-02

申请号：US501187

申请日：1995-07-11

申请人： Megumi Suzuki ,  Kazuhiro Tsuruta ,  Akiyoshi Asai

发明人： Megumi Suzuki ,  Kazuhiro Tsuruta ,  Akiyoshi Asai

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/78654 ,  H01L21/7624 ,  H01L21/76267 ,  H01L21/76283

摘要： A semiconductor device of SOI structure formed by the mesa isolation method, which can sufficiently reduce the wiring capacitance even if the width of the isolation trench is large. An SOI layer which constitutes an element region is formed by forming a buried oxide film in a silicon substrate, forming an isolation trench in the buried oxide film and burying an isolating material in the isolation trench. By the formation of the SOI layer with the isolating material, a dummy SOI layer is formed in a field part other than the element region. Then, by the formation of a MOSFET gate wiring on the dummy SOI layer, the wiring capacitance is reduced. Furthermore, the dummy SOI layer is completely depleted when the MOSFET threshold value is applied to the gate wiring.

摘要翻译： 通过台面隔离方法形成的SOI结构的半导体器件，即使隔离沟槽的宽度大，也可以充分降低布线电容。 构成元件区域的SOI层通过在硅衬底中形成掩埋氧化膜形成，在掩埋氧化膜中形成隔离沟槽，并在隔离沟槽中埋设隔离材料。 通过形成具有隔离材料的SOI层，在元件区域以外的场部形成有伪SOI层。 然后，通过在虚设SOI层上形成MOSFET栅极布线，布线电容减小。 此外，当MOSFET门限值被施加到栅极布线时，虚设SOI层完全耗尽。

公开(公告)号：US5488243A

公开(公告)日：1996-01-30

申请号：US160885

申请日：1993-12-03

申请人： Kazuhiro Tsuruta ,  Hiroaki Himi ,  Akiyoshi Asai ,  Seiji Fujino

发明人： Kazuhiro Tsuruta ,  Hiroaki Himi ,  Akiyoshi Asai ,  Seiji Fujino

IPC分类号： H01L27/04 ,  H01L21/336 ,  H01L21/822 ,  H01L21/84 ,  H01L27/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/66825 ,  H01L29/78648 ,  H01L29/7881 ,  H01L29/7885

摘要： A semiconductor device of an SOIMOSFET comprising a semiconductor substrate, an insulating layer and a thin film single-crystalline semiconductor layer, the insulating layer containing a floating electrically conductive layer buried therein at a portion corresponding to the channel, the floating electrically conductive layer being electrically insulated from the other portions, the semiconductor device further comprising an electrode adjacent to the floating electrically conductive layer for applying a voltage by which an electric charge is injected into and stored in the floating electroconductive layer.

摘要翻译： 一种包括半导体衬底，绝缘层和薄膜单晶半导体层的SOIMOSFET的半导体器件，所述绝缘层包含在与沟道相对应的部分埋入其中的浮动导电层，所述浮动导电层是电 与其他部分绝缘，所述半导体器件还包括与浮动导电层相邻的电极，用于施加电压，通过该电压注入电荷并将其存储在浮置导电层中。

公开(公告)号：US20110180938A1

公开(公告)日：2011-07-28

申请号：US13005741

申请日：2011-01-13

申请人： Kazuya HIRASAWA ,  Yuuji Ootani ,  Akiyoshi Asai ,  Hirokazu Imai ,  Hiroyoshi Kunieda ,  Harumi Kodama ,  Masayuki Onishi ,  Ryo Sakaguchi ,  Kazumi Nakayoshi

发明人： Kazuya HIRASAWA ,  Yuuji Ootani ,  Akiyoshi Asai ,  Hirokazu Imai ,  Hiroyoshi Kunieda ,  Harumi Kodama ,  Masayuki Onishi ,  Ryo Sakaguchi ,  Kazumi Nakayoshi

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/4334 ,  C08G77/04 ,  C08G77/20 ,  C08L83/04 ,  H01L23/296 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49531 ,  H01L24/13 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  C08L83/00 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an electronic device, a silicone adhesive bonding first and second members is made from a composition comprising: (A) 100 parts by mass of an organopolysiloxane containing in one molecule at least two alkenyl groups and being free of silicon-bonded hydroxyl and alkoxy groups wherein the content of cyclic siloxanes having 4 to 20 siloxane units is at most 0.1 mass %; (B) an organopolysiloxane containing in one molecule at least two silicon-bonded hydrogen atoms and being free of an alkenyl group, and silicon-bonded hydroxyl and alkoxy groups; (C) at least 0.05 parts by mass of an adhesion promoter; (D) 100 to 2000 parts by mass of a thermally conductive filler; and (E) a hydrosilylation-reaction catalyst. (B) is contained such that the silicon-bonded hydrogen atoms is in the range of 0.5 to 10 mol per 1 mol of the alkenyl groups of (A), and the sum of (B) and (C) is 0.5 to 10 mass % of the sum of (A), (B) and (C).

摘要翻译： 在电子设备中，粘合第一和第二构件的硅氧烷粘合剂由以下组合物制成：（A）100质量份在一分子中含有至少两个烯基并且不含硅键合的羟基和烷氧基的有机聚硅氧烷 其中具有4〜20个硅氧烷单元的环状硅氧烷的含量为0.1质量％以下。 （B）在一个分子中含有至少两个与硅键合的氢原子并且不含烯基的有机聚硅氧烷和与硅键合的羟基和烷氧基; （C）至少0.05质量份粘合促进剂; （D）100〜2000质量份导热性填料; 和（E）氢化硅烷化反应催化剂。 包含（B），使得与（A）的链烯基相比，与硅键合的氢原子为0.5〜10摩尔的范围，（B）和（C）的和为0.5〜10质量％ （A），（B）和（C）的总和的百分比。

公开(公告)号：US5736770A

公开(公告)日：1998-04-07

申请号：US248002

申请日：1994-05-24

申请人： Akiyoshi Asai ,  Nobuyuki Ohya ,  Mitsutaka Katada

发明人： Akiyoshi Asai ,  Nobuyuki Ohya ,  Mitsutaka Katada

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/52 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48 ,  H01L27/02 ,  H01L29/34

CPC分类号： H01L29/41775 ,  H01L21/76895 ,  H01L21/823871 ,  H01L2924/0002

摘要： A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

摘要翻译： 一种半导体器件，包括：半导体衬底; 从半导体衬底的表面延伸到内部的扩散区域; 第一绝缘层，形成在半导体衬底上，并且具有位于该扩散区域被暴露的接触孔; 第一导体层，形成在所述第一绝缘层的一部分上，并且使所述扩散区域穿过所述第一接触孔连接; 以及由所述第一导体层的物质的氧化物构成并形成在所述第一绝缘层的另一部分上以包围所述第一导体层的绝缘体部。

公开(公告)号：US5869872A

公开(公告)日：1999-02-09

申请号：US974700

申请日：1997-11-19

申请人： Akiyoshi Asai ,  Jun Sakakibara ,  Megumi Suzuki ,  Seiji Fujino

发明人： Akiyoshi Asai ,  Jun Sakakibara ,  Megumi Suzuki ,  Seiji Fujino

IPC分类号： H01L27/04 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L23/62 ,  H01L27/01 ,  H01L27/76

CPC分类号： H01L27/0266 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a semiconductor element having a pn-junction is included in the semiconductor substrate. The semiconductor integrated circuit device having the SOI structure is formed with a semiconductor layer, or SOI layer, on a p-type semiconductor substrate through a buried insulating film and further with semiconductor circuit elements serving as functional elements at the SOI layer thus formed. As a protection transistor to protect the semiconductor circuit elements, a MOSFET may be formed in which n-type diffusion layers are formed in the semiconductor substrate. The n-type diffusion layers of the MOSFET are to be surrounded by p-type diffusion layers more highly doped than the semiconductor substrate.

摘要翻译： 具有SOI结构的半导体集成电路器件即使当具有pn结的半导体元件被包括在半导体衬底中时，也能够防止从扩散层流出的漏电流的发生。 具有SOI结构的半导体集成电路器件通过掩埋绝缘膜在p型半导体衬底上形成半导体层或SOI层，并且还在半导体电路元件作为这样形成的SOI层上的功能元件。 作为用于保护半导体电路元件的保护晶体管，可以形成在半导体衬底中形成n型扩散层的MOSFET。 MOSFET的n型扩散层将被比半导体衬底更高掺杂的p型扩散层包围。

公开(公告)号：US5786616A

公开(公告)日：1998-07-28

申请号：US926997

申请日：1997-09-10

申请人： Harutsugu Fukumoto ,  Hiroaki Tanaka ,  Akiyoshi Asai

发明人： Harutsugu Fukumoto ,  Hiroaki Tanaka ,  Akiyoshi Asai

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/0251 ,  H01L27/1203

摘要： A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed. An electrostatic withstand quantity of the inverter circuit can be increased.

摘要翻译： 公开了一种SOI半导体集成电路器件，其可以防止信号输入端子和其电源输入端子之间的浪涌以获得改善的静电耐受量。 作为集成电路的逆变器电路形成在通过p型硅衬底上的绝缘膜形成的薄膜半导体层中。 在硅衬底内形成n型二极管扩散区，电阻扩散区和FET扩散区。 反相器电路的输入部分通过电阻器扩散区域连接到信号输入端子IN。 电源输入端子VC通过由二极管扩散区形成的反向偏置二极管D连接到接地端子GND。 当浪涌被施加到信号输入端子IN时，由电阻器扩散区域和硅衬底组成的寄生二极管DD表现为雪崩击穿，旁路浪涌电压。 可以增加逆变器电路的静电耐受量。

公开(公告)号：US6150697A

公开(公告)日：2000-11-21

申请号：US301562

申请日：1999-04-29

申请人： Akihiko Teshigahara ,  Akiyoshi Asai ,  Kunihiro Onoda ,  Hiroyasu Itou ,  Ryuichirou Abe ,  Toshio Sakakibara

发明人： Akihiko Teshigahara ,  Akiyoshi Asai ,  Kunihiro Onoda ,  Hiroyasu Itou ,  Ryuichirou Abe ,  Toshio Sakakibara

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L27/01

CPC分类号： H01L29/66681 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0696 ,  H01L29/66674 ,  H01L29/7824 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  H01L29/402

摘要： An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

摘要翻译： 在SOI衬底中设置由沟槽包围的岛状区域。 岛区还被具有缓冲区接触层的缓冲区包围。 在岛状区域，源极区域围绕漏极区域环状设置，源极和漏极电极分别设置在源极和漏极区域上。 形成环形辅助电极，源电极在沟槽上延伸。 因此，施加到源电极的电压可以施加到辅助电极，使得缓冲区域和源电极之间的电场浓度被放宽。

公开(公告)号：US5279981A

公开(公告)日：1994-01-18

申请号：US868572

申请日：1992-04-15

申请人： Shigemitsu Fukatsu ,  Akiyoshi Asai

发明人： Shigemitsu Fukatsu ,  Akiyoshi Asai

IPC分类号： H01L21/316 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/324 ,  H01L27/11524 ,  H01L29/66825 ,  Y10S438/91

摘要： The present invention is intended to provide a method of fabricating an EEPROM having excellent endurance characteristics. A work obtained by processing a substrate (1) by a wafer processing process including a passivating process and having a tunnel oxide film, an aluminum wiring film and a passivation film is subjected to a low-temperature heat treatment employing a processing temperature of about 250.degree. C. and a processing time on the order of 50 hr in a thermostatic oven (20) in the presence of nitrogen gas. The low-temperature heat treatment reduces trap sites produced in the tunnel oxide film by a plasma CVD process carried out to form the passivation film to repair the tunnel oxide film damaged by the plasma CVD process and to improve the endurance characteristics. The aluminum wiring film is not deteriorated by the low-temperature heat treatment because the low-temperature heat treatment employs a relatively low processing temperature.

摘要翻译： 本发明旨在提供一种制造具有优异的耐久特性的EEPROM的方法。 对通过包括钝化处理并具有隧道氧化物膜，铝布线膜和钝化膜的晶片处理工艺处理衬底（1）而获得的工作进行使用约250的处理温度的低温热处理 并在氮气存在下在恒温炉（20）中处理约50小时的处理时间。 低温热处理通过等离子体CVD工艺在隧道氧化物膜中产生的陷阱位置减少以形成钝化膜，以修复由等离子体CVD工艺损坏的隧道氧化膜并提高耐久性。 由于低温热处理采用相对低的处理温度，所以铝布线膜不会因低温热处理而劣化。