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    TESTING OF ELECTRONIC DEVICES THROUGH CAPACITIVE INTERFACE
    3.
    发明申请
    TESTING OF ELECTRONIC DEVICES THROUGH CAPACITIVE INTERFACE 有权
    通过电容接口测试电子设备

    公开(公告)号：US20110089962A1

    公开(公告)日：2011-04-21

    申请号：US12907839

    申请日：2010-10-19

    申请人： Alberto PAGANI

    发明人： Alberto PAGANI

    IPC分类号： G01R31/312 ,  G01R1/06 ,  G01R31/302

    CPC分类号： G01R1/06761 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/06733 ,  G01R1/06766 ,  G01R1/07 ,  G01R1/07314 ,  G01R31/312

    摘要： An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

    摘要翻译： 一种用于执行具有多个导电端子的电子装置的测试的测试装置的实施例，所述测试装置包括用于与端子交换电信号的多个导电测试探针，以及用于机械耦合 用电子设备测试探头。 在一个实施例中，耦合装置包括绝缘装置，用于在执行测试期间将至少部分测试探针中的每一个与至少一个相应的端子电绝缘。 每个测试探头和相应的端子形成用于将测试探头与端子电磁耦合的电容器。

    ELECTROMAGNETIC SHIELD FOR TESTING INTEGRATED CIRCUITS
    4.
    发明申请
    ELECTROMAGNETIC SHIELD FOR TESTING INTEGRATED CIRCUITS 有权
    用于测试集成电路的电磁屏蔽

    公开(公告)号：US20110050267A1

    公开(公告)日：2011-03-03

    申请号：US12851680

    申请日：2010-08-06

    申请人： Alberto PAGANI

    发明人： Alberto PAGANI

    IPC分类号： G01R31/00 ,  G01R1/06

    CPC分类号： G01R1/18 ,  G01R1/06772 ,  G01R1/07307 ,  G01R31/2884 ,  G01R31/2886

    摘要： An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

    摘要翻译： 提出了一种探针卡的实施例。 探针卡包括多个探针。 每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。 所述多个探头包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。 所述探针卡包括对应于所述至少一个探头的至少一个电磁屏蔽结构，所述至少一个探针适于提供和/或接收射频测试信号，用于对由至少一个探头照射的电磁场的至少部分屏蔽， /或接收射频测试信号。

    CONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT WITH CAPACITIVE FUNCTION
    6.
    发明申请
    CONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT WITH CAPACITIVE FUNCTION 有权
    具有电容功能的集成电路的连接结构

    公开(公告)号：US20130277803A1

    公开(公告)日：2013-10-24

    申请号：US13914820

    申请日：2013-06-11

    申请人： Alberto PAGANI

    发明人： Alberto PAGANI

    IPC分类号： H01L49/02

    CPC分类号： H01L28/90 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced.

    摘要翻译： 在单个结构中的一个实施例组合了包括适于将集成在芯片中的电路元件与芯片本身外部的电路和至少一个电容器耦合的连接端子的焊盘。 通过以单一结构组合连接焊盘和电容器，由于电容器本身的存在，可以减小芯片的总面积，否则在共同的集成电路中将会更大。 以这种方式，可以降低芯片的成本和尺寸。

    TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER
    7.
    发明申请
    TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER 有权
    电路集成在一个波形上的测试结构

    公开(公告)号：US20130026466A1

    公开(公告)日：2013-01-31

    申请号：US13554133

    申请日：2012-07-20

    申请人： Alberto PAGANI

    发明人： Alberto PAGANI

    IPC分类号： H01L23/544 ,  H01L21/768 ,  H01L29/02 ,  H01L23/525

    CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/12042 ,  H01L2924/00

    摘要： An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

    摘要翻译： 描述了晶片上的集成电路的测试架构的实施例，其包括在划线中实现的结构TEG的至少一个第一电路，其提供至少一个第一和第二集成电路之间的间隔。 该架构包括在这些第一和第二集成电路和第一电路中的至少一个内的第二电路共享的至少一个焊盘，以及耦合到至少一个焊盘和这些第一和第二电路的开关电路。

    PROBES FOR TESTING INTEGRATED ELECTRONIC CIRCUITS AND CORRESPONDING PRODUCTION METHOD
    9.
    发明申请
    PROBES FOR TESTING INTEGRATED ELECTRONIC CIRCUITS AND CORRESPONDING PRODUCTION METHOD 有权
    用于测试集成电子电路的探针和相应的生产方法

    公开(公告)号：US20110279137A1

    公开(公告)日：2011-11-17

    申请号：US13106615

    申请日：2011-05-12

    申请人： Alberto PAGANI

    发明人： Alberto PAGANI

    IPC分类号： G01R1/067 ,  G01R3/00 ,  G01R31/20

    CPC分类号： G01R3/00 ,  G01R1/06761 ,  G01R1/07307 ,  G01R1/07342 ,  G01R31/31905 ,  Y10T29/49002

    摘要： An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

    摘要翻译： 提出了一种用于制造用于集成电子电路的测试装置的悬臂探针的方法的实施例; 探针被配置为在测试的电子电路的相应端子的测试期间接触。 一个实施例包括形成导电材料的探针体。 在一个实施例中，该方法还包括在每个探针体的下部形成在使用中的，被引导到要接触的相应端子的第一硬度值等于或大于300HV的导电接触区域; 每个接触区域和相应的探针体形成相应的探针。