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    Replacement of scribeline padframe with saw-friendly design
    1.
    发明授权
    Replacement of scribeline padframe with saw-friendly design 有权
    用锯切友好的设计更换模板衬垫

    公开(公告)号：US08309957B2

    公开(公告)日：2012-11-13

    申请号：US12759005

    申请日：2010-04-13

    申请人： Basab Chatterjee ,  Jeffrey Alan West ,  Gregory Boyd Shinn

    发明人： Basab Chatterjee ,  Jeffrey Alan West ,  Gregory Boyd Shinn

    IPC分类号： H01L23/50

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2224/05093

    摘要： An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

    摘要翻译： 一种集成电路基板，其包含在切割切割车道上方并且在其两侧的电探针焊盘结构。 电探针焊盘结构包括与切割切口通道相邻的金属裂纹阻止条。 断裂条之间的金属密度小于70％。 包含金属裂纹阻挡带的电探针垫结构，裂纹阻挡带之间的金属密度小于70％。 通过在与集成电路相邻的切割切口通道上形成电探针焊盘结构来形成集成电路的工艺，使得电探针焊盘结构具有与切割锯缝通道相邻的金属裂纹阻挡条，并且通过 电探针垫结构。

    Crack deflector structure for improving semiconductor device robustness against saw-induced damage
    2.
    发明授权
    Crack deflector structure for improving semiconductor device robustness against saw-induced damage 有权
    裂纹偏转器结构，用于提高半导体器件对锯损坏的鲁棒性

    公开(公告)号：US08912076B2

    公开(公告)日：2014-12-16

    申请号：US12613175

    申请日：2009-11-05

    申请人： Jeffrey Alan West ,  Thomas D. Bonifield ,  Basab Chatterjee

    发明人： Jeffrey Alan West ,  Thomas D. Bonifield ,  Basab Chatterjee

    IPC分类号： H01L23/58 ,  H01L23/00

    CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

    摘要翻译： 一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。 裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。 连续金属层不延伸经过连续接触和连续通孔。 连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面 划线或裂纹偏转划痕。

    Warpage control for die with protruding TSV tips during thermo-compressive bonding
    3.
    发明授权
    Warpage control for die with protruding TSV tips during thermo-compressive bonding 有权
    在热压缩粘合时具有突出TSV端头的模具的翘曲控制

    公开(公告)号：US08298944B1

    公开(公告)日：2012-10-30

    申请号：US13150873

    申请日：2011-06-01

    申请人： Jeffrey Alan West

    发明人： Jeffrey Alan West

    IPC分类号： H01L21/44 ,  H01L29/40 ,  H01L23/52 ,  H01L21/768 ,  H01L23/538

    CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A method of fabricating through silicon via (TSV) die includes depositing a first dielectric layer on a substrate that includes a plurality of TSV die. The TSV die have a topside including active circuitry, a bottomside, and a plurality of TSVs including an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. The first dielectric layer covers the TSV tips. A portion of the first dielectric layer is removed to expose the TSV tips. At least one metal layer is deposited on the TSV tips to form metal caps on the TSV tips to provide metal capped TSV tips. A second dielectric layer is deposited on the bottomside of the substrate to cover the metal capped TSV tips. A portion of the second dielectric layer is removed to expose a portion of the metal capped TSV tips.

    摘要翻译： 通过硅通孔（TSV）晶片制造的方法包括在包括多个TSV晶片的衬底上沉积第一介电层。 TSV管芯具有包括有源电路，底部和多个TSV的顶面，其包括从顶侧到达从底部延伸出的突出的TSV尖端的内部金属芯。 第一介电层覆盖TSV尖端。 去除第一电介质层的一部分以暴露TSV尖端。 至少一个金属层沉积在TSV尖端上以在TSV尖端上形成金属盖，以提供金属封盖的TSV尖端。 第二电介质层沉积在衬底的底部以覆盖金属封盖的TSV尖端。 去除第二电介质层的一部分以露出金属封盖的TSV尖端的一部分。

    Semiconductor device having enhanced scribe and method for fabrication
    4.
    发明授权
    Semiconductor device having enhanced scribe and method for fabrication 有权
    具有增强的划片和制造方法的半导体器件

    公开(公告)号：US08125054B2

    公开(公告)日：2012-02-28

    申请号：US12565748

    申请日：2009-09-23

    申请人： Jeffrey Alan West ,  Craig Beddingfield

    发明人： Jeffrey Alan West ,  Craig Beddingfield

    IPC分类号： H01L23/544 ,  H01L21/00

    CPC分类号： H01L23/585 ,  H01L23/3114 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe seal follows the perimeter of the die and into the corners, with the outer scribe seal having a continuous barrier wall towards the die edges so that moisture penetration in dielectric layers of the die is minimized, and cracks and delamination are stopped near the die edges. Limiting the extent of the insulating layer or layers in the WLCSP to cover the functional circuit area also reduces the stresses caused by these layers near the die corners.

    摘要翻译： 在用于晶片级芯片级封装（WLCSP）的半导体器件和制造方法中，在不会一直延伸到矩形裸片的角部的功能电路区域周围形成内划线密封，并且 外部划片密封件遵循模具的周边并进入拐角，外部划片密封件具有朝向模具边缘的连续的阻挡壁，使得模具的电介质层中的水分渗透最小化，并且在模具附近停止裂纹和分层 边缘。 限制WLCSP中绝缘层或层的覆盖功能电路面积的程度也减少了这些层在模角附近引起的应力。

    IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS
    5.
    发明申请
    IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS 有权
    具有降低TSV诱导应力的TSV阵列IC

    公开(公告)号：US20100171226A1

    公开(公告)日：2010-07-08

    申请号：US12648871

    申请日：2009-12-29

    申请人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

    发明人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

    IPC分类号： H01L23/48

    CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

    摘要翻译： 集成电路（IC）包括其上具有有源电路的顶面的衬底，其上包括多个金属互连级，包括第一金属互连级和顶金属互连级，以及底侧。 至少一个TSV阵列包括多个TSV。 TSV定位成包括多个内部行和一对外部行以及包括多个内部列和一对外部列的多个列的行。 阵列中的TSV的至少一部分是电连接的TSV，其被耦合到从多个金属互连级别中选择的TSV端接金属互连级别。 与内部行和内部列中的最多数量的电连接的TSV相比，外部列或外部列中的至少一个包括较少数量的电连接的TSV。

    Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness
    6.
    发明申请
    Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness 审中-公开
    用于制造具有嵌入式互连结构以提高模角坚固性的半导体器件的方法

    公开(公告)号：US20080290340A1

    公开(公告)日：2008-11-27

    申请号：US11805325

    申请日：2007-05-23

    申请人： Jeffrey Alan West

    发明人： Jeffrey Alan West

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L29/0657 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method for fabricating a semiconductor device a redundant scribe seal structure is formed. The semiconductor device includes a die having a rectangular shape with sloped corners. A scribe seal is formed to surround the die, the scribe seal having sides to form sloped corners that match the sloped corners of the die. A scribe seal extension having sharp corners is formed by extending the sides of the scribe seal that have a perpendicular orientation towards one another. The scribe seal extension redundantly encloses a corresponding one of the sloped corners of the scribe seal.

    摘要翻译： 在制造半导体器件的方法中，形成冗余划线密封结构。 半导体器件包括具有倾斜角的矩形形状的模具。 形成划线密封以围绕模具，划线密封件具有侧面以形成与模具的倾斜角匹配的倾斜角。 具有尖角的划痕密封件延伸部通过将划线密封件的侧面彼此延伸而形成。 划线密封延伸部冗余地包围划线密封件的相应一个倾斜角部。

    IC having TSV arrays with reduced TSV induced stress
    9.
    发明授权
    IC having TSV arrays with reduced TSV induced stress 有权
    IC具有减少TSV诱导应力的TSV阵列

    公开(公告)号：US08097964B2

    公开(公告)日：2012-01-17

    申请号：US12648871

    申请日：2009-12-29

    申请人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

    发明人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

    摘要翻译： 集成电路（IC）包括其上具有有源电路的顶面的衬底，其上包括多个金属互连级，包括第一金属互连级和顶金属互连级，以及底侧。 至少一个TSV阵列包括多个TSV。 TSV定位成包括多个内部行和一对外部行以及包括多个内部列和一对外部列的多个列的行。 阵列中的TSV的至少一部分是电连接的TSV，其被耦合到从多个金属互连级别中选择的TSV端接金属互连级别。 与内部行和内部列中的最多数量的电连接的TSV相比，外部列或外部列中的至少一个包括较少数量的电连接的TSV。