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    Wide and narrow trench formation in high aspect ratio MEMS
    2.
    发明申请
    Wide and narrow trench formation in high aspect ratio MEMS 有权
    宽和窄沟槽形成在高纵横比MEMS

    公开(公告)号：US20070026636A1

    公开(公告)日：2007-02-01

    申请号：US11192198

    申请日：2005-07-27

    申请人： Bishnu Gogoi

    发明人： Bishnu Gogoi

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： G01C19/5719 ,  B81B2201/0242 ,  B81C1/00063

    摘要： Methods have been provided for forming both wide and narrow trenches on a high-aspect ratio microelectromechanical (MEM) device on a substrate including a substrate layer (126), an active layer (128), and a first sacrificial layer (130) disposed at least partially therebetween. The method includes the steps of forming a first trench (154), a second trench (156), and a third trench (152) in the active layer (128), each trench (154, 156, 152) having an opening and sidewalls defining substantially equal first trench widths, depositing oxide and sacrificial layers thereover and removing the oxide and sacrificial layers to expose the third trench (152) and form a fourth trench (190) in the active layer (128) from the first and the second trench (154, 156), the fourth trench (190) having sidewalls defining a second trench width that is greater than the first trench width.

    摘要翻译： 已经提供了用于在包括衬底层（126），有源层（128）和第一牺牲层（130）的基板上的高纵横比微机电（MEM）器件上形成宽沟槽和窄沟槽的方法， 其间最少部分。 该方法包括以下步骤：在有源层（128）中形成第一沟槽（154），第二沟槽（156）和第三沟槽（152），每个沟槽（154,156,152）具有开口和侧壁 限定基本相等的第一沟槽宽度，在其上沉积氧化物和牺牲层，并且去除氧化物层和牺牲层以暴露第三沟槽（152）并且在有源层（128）中从第一和第二沟槽（152）形成第四沟槽（190） （154,156），所述第四沟槽（190）具有限定大于所述第一沟槽宽度的第二沟槽宽度的侧壁。

    Microelectronic assembly
    4.
    发明授权
    Microelectronic assembly 有权
    微电子组装

    公开(公告)号：US07723821B2

    公开(公告)日：2010-05-25

    申请号：US12186224

    申请日：2008-08-05

    申请人： Bishnu Gogoi

    发明人： Bishnu Gogoi

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

    摘要翻译： 提供微电子组件及其形成方法。 该方法包括在具有第一和第二相对表面（22,24）的半导体衬底（20）中形成第一和第二横向蚀刻停止壁（44,46）。 电感器（56）形成在半导体衬底（20）的第一表面（22）上，并且通过衬底（20）的第二表面（24）形成孔（60），以将衬底（20）暴露在衬底 第一和第二横向蚀刻停止壁（44,46）。 衬底（20）通过蚀刻孔（60）在第一和第二横向蚀刻停止壁（44,46）之间各向同性地蚀刻，以在半导体衬底（20）内形成空腔62。 密封层（70）形成在蚀刻孔（60）上方以密封空腔（62）。

    Microelectronic assembly and method for forming the same
    5.
    发明申请
    Microelectronic assembly and method for forming the same 有权
    微电子组装及其形成方法

    公开(公告)号：US20070075394A1

    公开(公告)日：2007-04-05

    申请号：US11239986

    申请日：2005-09-30

    申请人： Bishnu Gogoi

    发明人： Bishnu Gogoi

    IPC分类号： H01L29/00 ,  H01L21/465

    CPC分类号： H01L21/764 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls in a semiconductor substrate having first and second opposing surfaces. An inductor is formed on the first surface of the semiconductor substrate and a hole is formed through the second surface of the substrate to expose the substrate between the first and second lateral etch stop walls. The substrate is isotropically etched between the first and second lateral etch stop walls through the etch hole to create a cavity within the semiconductor substrate. A sealing layer is formed over the etch hole to seal the cavity.

    摘要翻译： 提供微电子组件及其形成方法。 该方法包括在具有第一和第二相对表面的半导体衬底中形成第一和第二横向蚀刻停止壁。 电感器形成在半导体衬底的第一表面上，并且穿过衬底的第二表面形成孔，以暴露第一和第二侧面蚀刻停止壁之间的衬底。 通过蚀刻孔在第一和第二横向蚀刻停止壁之间各向同性地蚀刻衬底，以在半导体衬底内形成空腔。 在蚀刻孔上形成密封层以密封空腔。

    Method of making a microelectromechanical (MEM) device using porous material as a sacrificial layer
    6.
    发明申请
    Method of making a microelectromechanical (MEM) device using porous material as a sacrificial layer 审中-公开
    制造使用多孔材料作为牺牲层的微机电（MEM）装置的方法

    公开(公告)号：US20060115919A1

    公开(公告)日：2006-06-01

    申请号：US11000547

    申请日：2004-11-30

    申请人： Bishnu Gogoi ,  Jin Zheng

    发明人： Bishnu Gogoi ,  Jin Zheng

    IPC分类号： H01L21/00 ,  H01L21/302

    CPC分类号： B81C1/00476 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0115 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

    摘要： A method of making a microelectromechanical (MEM) device using a standard silicon wafer, rather than an SOI wafer, includes selectively implanting a dopant in regions of the standard wafer, to thereby form heavily doped regions therein. The heavily doped regions are then converted to porous silicon regions. An electrical isolation layer is selectively deposited on the wafer and over a portion of one or more of the porous silicon regions. An epitaxial layer is grown over the porous silicon regions and the electrical isolation area, and device elements are formed in the epitaxial layer. Thereafter, at least portions of the porous silicon regions are removed, to thereby release the formed device elements.

    摘要翻译： 使用标准硅晶片而不是SOI晶片制造微机电（MEM）器件的方法包括在标准晶片的区域中选择性地注入掺杂剂，从而在其中形成重掺杂区域。 然后将重掺杂区域转换成多孔硅区域。 电绝缘层被选择性地沉积在晶片上以及一个或多个多孔硅区域的一部分上。 在多孔硅区域和电隔离区域上生长外延层，并且在外延层中形成器件元件。 此后，去除多孔硅区域的至少一部分，从而释放所形成的器件元件。

    MEM structure having reduced spring stiction
    7.
    发明申请
    MEM structure having reduced spring stiction 失效
    具有降低的弹性粘度的MEM结构

    公开(公告)号：US20050229706A1

    公开(公告)日：2005-10-20

    申请号：US10828042

    申请日：2004-04-20

    申请人： Jan Vandemeer ,  Bishnu Gogoi ,  Jonathan Hammond

    发明人： Jan Vandemeer ,  Bishnu Gogoi ,  Jonathan Hammond

    IPC分类号： B81B3/00 ,  G01P15/08 ,  G01P15/125

    CPC分类号： B81B3/001 ,  B81B2201/0235 ,  G01P15/08 ,  G01P15/125

    摘要： A micro-electromechanical (MEM) device has a folded tether spring in which each fold of the spring is surrounded by a rigidly fixed inner structure and outer structure. The fixed inner structure increases restoring force of the spring. The rigidly fixed inner and outer structures each have a major surface that include a plurality of notches of fixed width relative to a distance between the major surface and the spring. Additionally in one form extensions from the major surface of the rigidly fixed inner and outer structures are provided at distal ends thereof to make initial contact with the spring. The notches of the MEM device both reduce surface area contact with the spring and wick moisture away from the spring to minimize stiction.

    摘要翻译： 微机电（MEM）装置具有折叠的系绳弹簧，弹簧的每个折叠由刚性固定的内部结构和外部结构包围。 固定的内部结构增加了弹簧的恢复力。 刚性固定的内外结构各自具有主表面，该主表面包括相对于主表面和弹簧之间的距离具有固定宽度的多个凹口。 此外，在一个形式中，刚性固定的内外结构的主表面的延伸部设置在其远端处以与弹簧初始接触。 MEM器件的凹口都减少了与弹簧的表面积接触，并使芯吸湿度远离弹簧以最小化粘性。

    Release etch method for micromachined sensors
    8.
    发明授权
    Release etch method for micromachined sensors 有权
    微机械传感器的释放蚀刻方法

    公开(公告)号：US06770506B2

    公开(公告)日：2004-08-03

    申请号：US10328944

    申请日：2002-12-23

    申请人： Bishnu Gogoi

    发明人： Bishnu Gogoi

    IPC分类号： H01L2100

    CPC分类号： B81C1/00476 ,  B81B2201/033 ,  B81B2203/033 ,  B81B2203/051 ,  B81B2207/07 ,  B81C1/00626

    摘要： A method for creating a MEMS structure (100) is provided. In accordance with the method, an article is provided comprising a substrate (101), a sacrificial layer (103) and a semiconductor layer (105), wherein the sacrificial layer comprises a first material such as silicon oxide. A MEMS structure is then formed in the semiconductor layer. The structure has first (107) and second (109) elements which have an exposed portion of the sacrificial layer (103) disposed between them. The first element is then released from the substrate (101) by contacting the exposed portion of the sacrificial layer (103) with a first etchant, typically by way of one or more trenches (119), after which the first element is reattached to the substrate (101) with a second material (131). The first element is then released from the substrate (101) by contacting the second material (131) with a second etchant.

    摘要翻译： 提供了一种用于创建MEMS结构（100）的方法。 根据该方法，提供了一种包括衬底（101），牺牲层（103）和半导体层（105）的制品，其中所述牺牲层包括诸如氧化硅的第一材料。 然后在半导体层中形成MEMS结构。 该结构具有第一（107）和第二（109）元件，其具有设置在它们之间的牺牲层（103）的暴露部分。 然后通过将牺牲层（103）的暴露部分与第一蚀刻剂（通常通过一个或多个沟槽（119））接触将第一元件从衬底（101）释放，之后将第一元件重新连接到 衬底（101）与第二材料（131）。 然后通过使第二材料（131）与第二蚀刻剂接触来将第一元件从基板（101）释放。

    VERTICAL TRANSISTOR WITH FLASHOVER PROTECTION
    9.
    发明申请
    VERTICAL TRANSISTOR WITH FLASHOVER PROTECTION 有权
    带FLASHOVER保护的垂直晶体管

    公开(公告)号：US20160155734A1

    公开(公告)日：2016-06-02

    申请号：US14761599

    申请日：2014-04-01

    申请人： Bishnu Gogoi

    发明人： Bishnu Gogoi

    IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/0251 ,  H01L27/0248 ,  H01L29/0692 ,  H01L29/66666 ,  H01L29/7827

    摘要： Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In some examples, active silicon (at drain potential) may be removed at an edge of the die in the scribe grid so that the active silicon is approximately below a surface of the edge termination formed by a region of deep dielectric filled trenches. The recessed drain region at the edge of the die may increase a flashover distance without appreciably increasing the die size. Thus, a distance between the recessed drain region and the surface source region may be increased by a combination of vertical and lateral spacing resulting in a smaller overall die size and smaller parasitic capacitances when operated with substantially the same operating voltage.

    摘要翻译： 通常描述技术用于增加垂直高压晶体管的源极和漏极区域之间的间隔，而不会显着相应地增加管芯尺寸。 在一些实例中，活性硅（在漏极电位处）可以在划线栅格中的管芯的边缘处去除，使得活性硅大致低于由深电介质填充的沟槽的区域形成的边缘终端的表面。 在模具边缘处的凹陷漏极区域可以增加闪络距离，而不会明显增加管芯尺寸。 因此，通过垂直和横向间隔的组合可以增加凹陷漏极区域和表面源极区域之间的距离，导致当以基本上相同的工作电压操作时，更小的总管芯尺寸和更小的寄生电容。

    THREE-AXIS INERTIAL SENSOR AND METHOD OF FORMING
    10.
    发明申请
    THREE-AXIS INERTIAL SENSOR AND METHOD OF FORMING 有权
    三轴惯性传感器及其形成方法

    公开(公告)号：US20080053229A1

    公开(公告)日：2008-03-06

    申请号：US11848301

    申请日：2007-08-31

    申请人： Bishnu Gogoi ,  Navid Yazdi

    发明人： Bishnu Gogoi ,  Navid Yazdi

    IPC分类号： G01P15/125 ,  H01R43/00

    CPC分类号： G01P15/125 ,  G01P15/0802 ,  G01P15/18 ,  G01P2015/0814 ,  G01P2015/0828 ,  Y10T29/49117

    摘要： A three-axis inertial sensor and a process for its fabrication using an silicon-on-oxide (SOI) wafer as a starting material. The SOI wafer has a first conductive layer separated from a second conductive layer by an insulative buried oxide (BOX) layer. The SOI wafer is fabricated to partially define in its first conductive layer at least portions of proof masses for z, x, and y-axis sensing devices of the sensor. After a conductive deposited layer is deposited and patterned to form a suspension spring for the proof mass of the z-axis sensing device, the SOI wafer is bonded to a substrate that preferably carries interface circuitry for the z, x, and y-axis devices, with the SOI wafer being oriented so that its first conductive layer faces the substrate. Portions of the BOX layer are then etched to fully release the proof masses.

    摘要翻译： 三轴惯性传感器及其使用硅氧化物（SOI）晶片作为起始材料的制造方法。 SOI晶片具有通过绝缘掩埋氧化物（BOX）层与第二导电层分离的第一导电层。 制造SOI晶片以在其第一导电层中部分地限定传感器的z，x和y轴感测装置的至少一部分证明质量。 在沉积导电沉积层并图案化以形成用于z轴感测装置的检验质量块的悬浮弹簧之后，SOI晶片被结合到衬底，该衬底优选地承载用于z轴，x轴和y轴装置的接口电路 ，其中SOI晶片被定向成使得其第一导电层面向衬底。 然后蚀刻BOX层的部分以完全释放证明质量。