公开(公告)号：US20150171028A1

公开(公告)日：2015-06-18

申请号：US14492556

申请日：2014-09-22

Applicant: CHAJEA JO ,  Taeje CHO ,  YUNHYEOK IM

Inventor： CHAJEA JO ,  Taeje CHO ,  YUNHYEOK IM

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package is provided. At least one semiconductor chip is mounted on a package substrate. A mold layer covers the at least one semiconductor chip. The mold layer exposes a portion of a top surface of an uppermost semiconductor chip of the at least one semiconductor chip.

Abstract translation: 提供半导体封装。 至少一个半导体芯片安装在封装衬底上。 模具层覆盖至少一个半导体芯片。 模层暴露至少一个半导体芯片的最上半导体芯片的顶表面的一部分。

公开(公告)号：US20120119346A1

公开(公告)日：2012-05-17

申请号：US13243996

申请日：2011-09-23

Applicant: YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

Inventor： YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/29 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00

Abstract: Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a package cap which is capable of radiating high temperatures and performs a shield function preventing transmission of electromagnetic waves into and/or out of the semiconductor package. The semiconductor package including the package cap prevents chip malfunctions and improves device reliability. The package cap is positioned to cover first and second semiconductor chips of a semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括封装帽，其能够辐射高温并执行屏蔽功能，防止电磁波进入和/或流出半导体封装。 包括封装盖的半导体封装防止芯片故障并提高器件的可靠性。 封装帽定位成覆盖半导体封装的第一和第二半导体芯片。

公开(公告)号：US20140136827A1

公开(公告)日：2014-05-15

申请号：US14059428

申请日：2013-10-21

Applicant: EUNSEOK CHO ,  JAE CHOON KIM ,  YUNHYEOK IM

Inventor： EUNSEOK CHO ,  JAE CHOON KIM ,  YUNHYEOK IM

IPC: G06F9/50 ,  G01K7/01

CPC classification number: G01K7/01 ,  G01K13/00 ,  G06F1/206

Abstract: According to one general aspect, a data communication method may include detecting a temperature using a temperature sensor. The method may include selecting a bandwidth for data communications by a semiconductor integrated circuit based, at least in part, upon the detected temperature. The method may also include performing the communication of data based, at least in part, on the selected bandwidth.

Abstract translation: 根据一个一般方面，数据通信方法可以包括使用温度传感器检测温度。 该方法可以包括至少部分地基于检测到的温度来选择半导体集成电路进行数据通信的带宽。 该方法还可以包括至少部分地基于所选择的带宽来执行数据的通信。

公开(公告)号：US20170047264A1

公开(公告)日：2017-02-16

申请号：US15235958

申请日：2016-08-12

Applicant: YUNHYEOK IM ,  OLEG FEYGENSON ,  SANG IL KIM ,  YOUNGBAE KIM ,  JICHUL KIM ,  SEUNGKON MOK ,  JUNGSU HA

Inventor： YUNHYEOK IM ,  OLEG FEYGENSON ,  SANG IL KIM ,  YOUNGBAE KIM ,  JICHUL KIM ,  SEUNGKON MOK ,  JUNGSU HA

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.

Abstract translation: 公开了半导体封装及其制造方法。 半导体封装可以包括封装衬底，半导体芯片，其安装在封装衬底上以具有面向封装衬底的底表面和与底表面相对的顶表面;模具层，设置在封装衬底上以封装 半导体芯片和设置在半导体芯片的顶表面上的散热层。 模具层可以具有与半导体芯片的顶表面基本上共面的顶表面，并且半导体芯片和模具层的顶表面可以具有彼此不同的表面粗糙度。

公开(公告)号：US20140339708A1

公开(公告)日：2014-11-20

申请号：US14243165

申请日：2014-04-02

Applicant: Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

Inventor： Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

IPC: H01L23/34 ,  H01L23/12 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29194 ,  H01L2224/2929 ,  H01L2224/29309 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Abstract translation: 半导体封装器件包括下封装，其包括安装在下封装基板上的下半导体芯片，设置在下封装基板上的下模塑复合层，形成在下模塑复合层中以围绕下半导体芯片的第一沟槽，以及 连接到所述第一沟槽以延伸到所述下封装的外壁的第二沟槽，所述第二沟槽形成在所述下模塑复合层中，所述上封装设置在所述下封装上。 上封装包括上封装基板和安装在上封装基板上的至少一个上半导体芯片和设置在下封装和上封装之间的传热构件。

公开(公告)号：US20150115467A1

公开(公告)日：2015-04-30

申请号：US14457094

申请日：2014-08-11

Applicant: Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

Inventor： Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

IPC: H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/141 ,  H05K2201/10378 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Abstract translation: 本发明的概念提供了封装封装（PoP）器件。 在PoP器件中，可以在下半导体封装和上半导体封装之间设置插入器衬底和热边界材料层，以快速排出由下半导体封装中包括的下半导体芯片产生的热。 插入器基板可以由一个或多个绝缘层，导电通孔，散热构件，保护层和各种导电图案形成。

公开(公告)号：US20140367860A1

公开(公告)日：2014-12-18

申请号：US14185394

申请日：2014-02-20

Applicant: YUNHYEOK IM ,  JICHUL KIM ,  KYOL PARK ,  SEONGHO SHIN

Inventor： YUNHYEOK IM ,  JICHUL KIM ,  KYOL PARK ,  SEONGHO SHIN

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract translation: 半导体封装包括下封装，其包括在下封装基板上的下半导体芯片，下封装上的上封装，以及下封装和上封装之间的热界面材料。 上封装包括在上封装基板上的上半导体芯片，其包括与下半导体芯片相邻的中心部分和边缘部分。 热界面材料与下半导体芯片和上封装衬底的顶表面接触。 上封装衬底包括穿过中心部分的热扩散，以及穿过边缘部分的互连。 互连通孔与热扩散通孔间隔开。