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公开(公告)号：US08680647B2
公开(公告)日：2014-03-25
申请号：US13464081
申请日：2012-05-04
申请人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin
发明人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L23/64
CPC分类号： H01L21/56 , H01L23/3192 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L23/64 , H01L24/19 , H01L27/016 , H01L28/00 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/18162 , H01L2924/19011 , H01L2924/1903 , H01L2924/19031 , H01L2924/19033 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00012 , H01L2924/00
摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
摘要翻译： 一种器件包括衬底，衬底上的金属焊盘以及具有在金属焊盘上的部分的钝化层。 后钝化互连（PPI）线设置在钝化层上并电耦合到金属焊盘。 爆炸性冶金（UBM）被布置在电气耦合到PPI线路上。 无源设备包括与UBM处于相同水平的部分。 无源器件的部分由与UBM相同的材料形成。
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公开(公告)号：US20130168805A1
公开(公告)日：2013-07-04
申请号：US13464081
申请日：2012-05-04
申请人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin
发明人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin
CPC分类号： H01L21/56 , H01L23/3192 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L23/64 , H01L24/19 , H01L27/016 , H01L28/00 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/18162 , H01L2924/19011 , H01L2924/1903 , H01L2924/19031 , H01L2924/19033 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00012 , H01L2924/00
摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
摘要翻译： 一种器件包括衬底，衬底上的金属焊盘以及具有在金属焊盘上的部分的钝化层。 后钝化互连（PPI）线设置在钝化层上并电耦合到金属焊盘。 爆炸性冶金（UBM）被布置在电气耦合到PPI线路上。 无源设备包括与UBM处于相同水平的部分。 无源器件的部分由与UBM相同的材料形成。
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公开(公告)号：US08937389B2
公开(公告)日：2015-01-20
申请号：US13569017
申请日：2012-08-07
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/522 , H01L21/768 , H05K1/02
CPC分类号： H01L23/5226 , H01L21/76807 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L2924/0002 , H05K1/0215 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。
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公开(公告)号：US20140042612A1
公开(公告)日：2014-02-13
申请号：US13569017
申请日：2012-08-07
CPC分类号： H01L23/5226 , H01L21/76807 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L2924/0002 , H05K1/0215 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。
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公开(公告)号：US20140042643A1
公开(公告)日：2014-02-13
申请号：US13572240
申请日：2012-08-10
申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L23/5381 , H01L21/486 , H01L21/563 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0345 , H01L2224/0348 , H01L2224/0361 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14515 , H01L2224/16237 , H01L2224/2919 , H01L2224/29191 , H01L2224/32225 , H01L2224/73204 , H01L2224/81424 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/83855 , H01L2224/92125 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/0665 , H01L2224/1144 , H01L2924/00
摘要： A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
摘要翻译： 提供了一种用于提供插入器的系统和方法。 一个实施例包括在第一区域和第二区域之间的划线区域上形成中介层晶片上的第一区域和第二区域。 然后，第一区域和第二区域通过位于划线区域上方的电路彼此连接。 在另一个实施例中，第一区域和第二区域可以彼此分离，然后在第一区域连接到第二区域之前封装在一起。
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公开(公告)号：US08810006B2
公开(公告)日：2014-08-19
申请号：US13572240
申请日：2012-08-10
申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
IPC分类号： H01L23/544 , H01L29/40
CPC分类号： H01L23/5381 , H01L21/486 , H01L21/563 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0345 , H01L2224/0348 , H01L2224/0361 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14515 , H01L2224/16237 , H01L2224/2919 , H01L2224/29191 , H01L2224/32225 , H01L2224/73204 , H01L2224/81424 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/83855 , H01L2224/92125 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/0665 , H01L2224/1144 , H01L2924/00
摘要： A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
摘要翻译： 提供了一种用于提供插入器的系统和方法。 一个实施例包括在第一区域和第二区域之间的划线区域上形成中介层晶片上的第一区域和第二区域。 然后，第一区域和第二区域通过位于划线区域上方的电路彼此连接。 在另一个实施例中，第一区域和第二区域可以彼此分离，然后在第一区域连接到第二区域之前封装在一起。
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公开(公告)号：US08575717B2
公开(公告)日：2013-11-05
申请号：US13090606
申请日：2011-04-20
申请人： Der-Chyang Yeh , Shang-Yun Hou
发明人： Der-Chyang Yeh , Shang-Yun Hou
IPC分类号： H01L29/86
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.
摘要翻译： 提供一种集成电路器件及其制造方法。 集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。 所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料 和空隙区域。
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公开(公告)号：US08765549B2
公开(公告)日：2014-07-01
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
IPC分类号： H01L21/8242
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US20130285200A1
公开(公告)日：2013-10-31
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US20120267753A1
公开(公告)日：2012-10-25
申请号：US13090606
申请日：2011-04-20
申请人： Der-Chyang Yeh , Shang-Yun Hou
发明人： Der-Chyang Yeh , Shang-Yun Hou
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.
摘要翻译： 提供一种集成电路器件及其制造方法。 集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。 所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料 和空隙区域。
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