公开(公告)号：US08963298B2

公开(公告)日：2015-02-24

申请号：US12769053

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US20110198737A1

公开(公告)日：2011-08-18

申请号：US12769024

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552 ,  H01L21/60

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

摘要翻译： 提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕 裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。 进一步提出如上所述的制造封装结构的方法。

公开(公告)号：US20110175210A1

公开(公告)日：2011-07-21

申请号：US12769053

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552 ,  H01L21/78

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US08736030B2

公开(公告)日：2014-05-27

申请号：US12769024

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

摘要翻译： 提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕 裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。 进一步提出如上所述的制造封装结构的方法。

公开(公告)号：US08198689B2

公开(公告)日：2012-06-12

申请号：US12769041

申请日：2010-04-28

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC分类号： H01L23/485

CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。

公开(公告)号：US08026602B2

公开(公告)日：2011-09-27

申请号：US12872164

申请日：2010-08-31

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/14104 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

摘要翻译： 提供了具有导电凸块的半导体器件及其制造方法。 该制造方法主要包括以下步骤：提供具有焊料焊盘和形成在其上的钝化层的半导体衬底，其中一部分焊料焊盘从钝化层暴露出来; 在焊料焊盘上设置第一金属层和围绕焊盘的钝化层的一部分; 在所述第一金属层和所述钝化层上设置覆盖层，以及在所述覆盖层中形成孔以暴露所述第一金属层的一部分，其中所述孔的中心偏离所述焊盘的中心; 在所述第一金属层的所述部分上沉积金属柱; 并在金属柱的外表面上沉积焊料，以提供更好的缓冲效果。

公开(公告)号：US20110156227A1

公开(公告)日：2011-06-30

申请号：US12770028

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/495

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

摘要翻译： 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

公开(公告)号：US07666779B2

公开(公告)日：2010-02-23

申请号：US12060379

申请日：2008-04-01

申请人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.

摘要翻译： 提供半导体器件及其制造方法。 制备具有多个接合焊盘的半导体衬底，并且在半导体衬底上依次形成第一钝化层，第二钝化层和金属层。 第三钝化层进一步施加在半导体衬底上并且具有用于暴露金属层的一部分的多个开口，其中每个开口从对应的一个焊盘移位一定距离不超过半径 的焊盘。 多个焊料凸点与金属层的露出部分接合，并且与第三钝化层具有较大的接触面积。 这提供了更好的缓冲器以减少施加在焊料凸块上的应力，从而防止了现有技术中的开裂和分层问题。

公开(公告)号：US20080182401A1

公开(公告)日：2008-07-31

申请号：US12060379

申请日：2008-04-01

申请人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.

摘要翻译： 提供半导体器件及其制造方法。 制备具有多个接合焊盘的半导体衬底，并且在半导体衬底上依次形成第一钝化层，第二钝化层和金属层。 第三钝化层进一步施加在半导体衬底上并且具有用于暴露金属层的一部分的多个开口，其中每个开口从对应的一个焊盘移位一定距离不超过半径 的焊盘。 多个焊料凸点与金属层的露出部分接合，并且与第三钝化层具有较大的接触面积。 这提供了更好的缓冲器以减少施加在焊料凸块上的应力，从而防止了现有技术中的开裂和分层问题。

公开(公告)号：US07358177B2

公开(公告)日：2008-04-15

申请号：US11190271

申请日：2005-07-26

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L2224/0401 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014

摘要： A fabrication method of under bump metallurgy (UBM) structure is provided. A blocking layer is applied over a surface of a semiconductor element formed with at least one bond pad and a passivation layer thereon. The passivation layer covers the semiconductor element and exposes the bond pad, and the blocking layer covers the bond pad and the passivation layer. The blocking layer is formed with at least one opening at a position corresponding to the bond pad. Metallic layers are formed on a surface of the blocking layer and at the opening. The metallic layers are patterned to form a UBM structure at the opening corresponding to the bond pad. Then the blocking layer is removed. The blocking layer can separate the metallic layers for forming the UBM structure from the passivation layer to prevent metallic residues of the UBM structure from being left on the passivation layer.

摘要翻译： 提供了一种凸块下冶金（UBM）结构的制造方法。 在其上形成有至少一个接合焊盘和钝化层的半导体元件的表面上施加阻挡层。 钝化层覆盖半导体元件并暴露接合焊盘，并且阻挡层覆盖接合焊盘和钝化层。 阻挡层在对应于接合焊盘的位置处形成有至少一个开口。 金属层形成在阻挡层的表面和开口处。 金属层被图案化以在对应于接合焊盘的开口处形成UBM结构。 然后去除阻挡层。 阻挡层可以将用于形成UBM结构的金属层与钝化层分开，以防止UBM结构的金属残留物残留在钝化层上。