公开(公告)号：US20060035471A1

公开(公告)日：2006-02-16

申请号：US11204509

申请日：2005-08-16

Applicant: Chris Hill ,  Weimin Li ,  Gurtej Sandhu

Inventor： Chris Hill ,  Weimin Li ,  Gurtej Sandhu

IPC: H01L21/336

CPC classification number: C23C16/45523 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31625

Abstract: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.

Abstract translation: 衬底位于沉积室内。 将至少两种气体前体进料到共同包含硅的室，包含氧和掺杂剂的氧化剂成为沉积的掺杂二氧化硅的一部分。 进料至少在两个不同的时间段内并且在有效沉积掺杂的二氧化硅层的条件下在基板上。 时间段和条件的特征在于一段时间，其中一种所述包含所述掺杂剂的气态前体在基本上不流动任何所述氧化剂前体的情况下流动到所述室。 在一个实施方案中，与沉积在限定所述间隙的衬底结构上的任何掺杂二氧化硅相比，时间段和条件有效地至少在衬底上的至少一些间隙内沉积更大量的掺杂二氧化硅。

公开(公告)号：US06368988B1

公开(公告)日：2002-04-09

申请号：US09354572

申请日：1999-07-16

Applicant: Weimin Li ,  Sujit Sharan ,  Gurtej Sandhu

Inventor： Weimin Li ,  Sujit Sharan ,  Gurtej Sandhu

IPC: H01L21318

CPC classification number: H01L29/6656 ,  C23C16/345 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

公开(公告)号：US20050056940A1

公开(公告)日：2005-03-17

申请号：US10661100

申请日：2003-09-12

Applicant: Gurtej Sandhu ,  Zhiping Yin ,  Weimin Li

Inventor： Gurtej Sandhu ,  Zhiping Yin ,  Weimin Li

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L29/40

CPC classification number: H01L21/3081 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10852

Abstract: A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer includes transparent amorphous carbon. The cap layer includes non-oxide materials. The masking structure may be used as a mask in an etching process during fabrication of semiconductor devices.

Abstract translation: 形成具有多层的掩模结构。 掩模结构包括无定形碳层和形成在无定形碳层上的盖层。 无定形碳层包括透明无定形碳。 盖层包括非氧化物材料。 在半导体器件的制造期间，掩模结构可以用作蚀刻工艺中的掩模。

公开(公告)号：US20050011449A1

公开(公告)日：2005-01-20

申请号：US10916918

申请日：2004-08-12

Applicant: Weimin Li ,  Neal Rueger ,  Li Li ,  Ross Dando ,  Kevin Hamer ,  Allen Mardian ,  Gurtej Sandhu

Inventor： Weimin Li ,  Neal Rueger ,  Li Li ,  Ross Dando ,  Kevin Hamer ,  Allen Mardian ,  Gurtej Sandhu

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/507 ,  C23C16/00

CPC classification number: C23C16/45565 ,  C23C16/455 ,  C23C16/507

Abstract: The present invention is generally directed to a novel gas delivery system for various deposition processes, and various methods of using same. In one illustrative embodiment, a deposition tool comprises a process chamber, a wafer stage adapted for holding a wafer positioned therein, and a gas delivery system positioned in the chamber above a position where a plasma will be generated in the chamber, wherein substantially all of a reactant gas is delivered into the chamber via the gas delivery system. In another illustrative embodiment, the reactant gas exiting the gas delivery system is directed so as to cover substantially all of an area defined by an upper surface of the wafer. In one illustrative embodiment, the method comprises positioning a wafer in a process chamber of a deposition tool, generating a plasma within the process chamber above the wafer, and forming a layer of material above the wafer by introducing substantially all of a reactant gas used to form the layer of material into the process chamber above the plasma via a gas delivery system positioned above the plasma. In another illustrative embodiment, the reactant gas exiting the gas delivery system is directed to cover substantially all of an area defined by an upper surface of the wafer.

Abstract translation: 本发明一般涉及用于各种沉积工艺的新型气体输送系统及其使用方法。 在一个说明性实施例中，沉积工具包括处理室，适于保持位于其中的晶片的晶片台，以及定位在室中的气体输送系统，其位于室内将产生等离子体的位置，其中基本上全部 反应气体通过气体输送系统输送到室中。 在另一说明性实施例中，离开气体输送系统的反应物气体被引导以覆盖由晶片的上表面限定的基本上所有的区域。 在一个示例性实施例中，该方法包括将晶片定位在沉积工具的处理室中，在晶片上方的处理室内产生等离子体，并且通过将基本上所有的反应气体基本上引入到 通过位于等离子体上方的气体输送系统将材料层形成在等离子体上方的处理室中。 在另一示例性实施例中，离开气体输送系统的反应物气体被引导以覆盖由晶片的上表面限定的基本上所有的区域。

公开(公告)号：US20060205236A1

公开(公告)日：2006-09-14

申请号：US11432739

申请日：2006-05-11

Applicant: Weimin Li ,  Gurtej Sandhu

Inventor： Weimin Li ,  Gurtej Sandhu

IPC: H01L21/31 ,  H01L21/469 ,  B32B9/04

CPC classification number: G03F7/095 ,  G03F7/0757 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/311 ,  Y10T428/31663

Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.

Abstract translation: 能够使光可图案化的旋涂材料用于以前不可用的波长形成半导体器件结构的盖层。 将可光刻图案的旋涂材料作为层施加到半导体衬底。 覆盖层和光致抗蚀剂层各自形成在光图案化层上。 盖层吸收或反射辐射，并保护光致图案层免受用于图案化光致抗蚀剂层的第一波长的辐射。 照射图案化的旋涂材料在暴露于第二波长辐射时可转换为二氧化硅基材料。

公开(公告)号：US20060076597A1

公开(公告)日：2006-04-13

申请号：US11235866

申请日：2005-09-26

Applicant: Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

Inventor： Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

IPC: H01L29/94

CPC classification number: H01L28/84 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

Abstract: Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

公开(公告)号：US20060001175A1

公开(公告)日：2006-01-05

申请号：US11215671

申请日：2005-08-30

Applicant: Gurtej Sandhu ,  Zhiping Yin ,  Weimin Li

Inventor： Gurtej Sandhu ,  Zhiping Yin ,  Weimin Li

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/3081 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10852

Abstract: A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer includes transparent amorphous carbon. The cap layer includes non-oxide materials. The masking structure may be used as a mask in an etching process during fabrication of semiconductor devices.

Abstract translation: 形成具有多层的掩模结构。 掩模结构包括无定形碳层和形成在无定形碳层上的盖层。 无定形碳层包括透明无定形碳。 盖层包括非氧化物材料。 在半导体器件的制造期间，掩模结构可以用作蚀刻工艺中的掩模。

公开(公告)号：US20050196976A1

公开(公告)日：2005-09-08

申请号：US11115854

申请日：2005-04-25

Applicant: Neal Rueger ,  William Budge ,  Weimin Li ,  Gurtej Sandhu

Inventor： Neal Rueger ,  William Budge ,  Weimin Li ,  Gurtej Sandhu

IPC: C23C16/04 ,  C23C16/40 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76224 ,  H01L21/76837

Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

Abstract translation: 本发明包括填充半导体衬底中的间隙的方法。 在反应室内设置底物和含有至少一种重氢化合物的气体混合物。 通过同时沉积和蚀刻该层，使气体混合物反应以在衬底上形成一层材料。 材料层填充间隙，使得间隙内的材料基本上无空隙。 本发明包括提供改进的沉积速率均匀性的方法。 在选自由D 2，HD，DT，T 2和TH组成的组中的至少一种气体存在下，材料沉积在表面上。 沉积期间的净沉积速率在整个表面上具有相对于在其它实质上相同的条件下利用H 2 N沉积期间发生的相应的变化程度可以显着改善的表面上的变化程度。

公开(公告)号：US20050064729A1

公开(公告)日：2005-03-24

申请号：US10669671

申请日：2003-09-23

Applicant: Neal Rueger ,  William Budge ,  Weimin Li ,  Gurtej Sandhu

Inventor： Neal Rueger ,  William Budge ,  Weimin Li ,  Gurtej Sandhu

IPC: C23C16/04 ,  C23C16/40 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/469

CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76224 ,  H01L21/76837

Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

Abstract translation: 本发明包括填充半导体衬底中的间隙的方法。 在反应室内设置底物和含有至少一种重氢化合物的气体混合物。 通过同时沉积和蚀刻该层，使气体混合物反应以在衬底上形成一层材料。 材料层填充间隙，使得间隙内的材料基本上无空隙。 本发明包括提供改进的沉积速率均匀性的方法。 在选自由D2，HD，DT，T2和TH组成的组中的至少一种气体的存在下，在表面上沉积材料。 沉积期间的净沉积速率在整个表面上具有相对于相对于在基本上相同的条件下利用H 2时沉积期间发生的相应的变化程度可以显着改善的表面的变化程度。

公开(公告)号：US06524975B2

公开(公告)日：2003-02-25

申请号：US09989036

申请日：2001-11-21

Applicant: Weimin Li ,  Sujit Sharan ,  Gurtej Sandhu

Inventor： Weimin Li ,  Sujit Sharan ,  Gurtej Sandhu

IPC: H01L21318

CPC classification number: H01L29/6656 ,  C23C16/345 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.