公开(公告)号：US08058102B2

公开(公告)日：2011-11-15

申请号：US12615682

申请日：2009-11-10

Applicant: Diann-Fang Lin ,  Yu-Shan Hu

Inventor： Diann-Fang Lin ,  Yu-Shan Hu

IPC: H01L21/48

CPC classification number: H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract translation: 本发明公开了一种具有再分配层（RDL）和硅通孔（TSV）技术的半导体器件封装结构。 封装结构包括电子元件，该电子元件包括在电子元件的背面上的电介质层，穿过电子元件和电介质层的多个第一导电通孔以及伴随第一导电通孔的多个导电垫 在电子元件的有效表面上; 设置在电子元件附近的填充材料; 设置在电介质层和填充材料之上并连接到第一导电通孔的第一再分配层; 设置在电子元件的有源表面上的第一保护层，导电焊盘和填充材料; 以及设置在再分布层，电介质层和填充材料之上的第二保护层。

公开(公告)号：US20110180891A1

公开(公告)日：2011-07-28

申请号：US12869001

申请日：2010-08-26

Applicant: Diann-Fang Lin ,  Yu-Shan Hu

Inventor： Diann-Fang Lin ,  Yu-Shan Hu

IPC: H01L31/0232

CPC classification number: H01L23/49827 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16195 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00

Abstract: The present invention provides a conductor package structure comprising an optical sensor element. A filling material is filled around the optical sensor element. At least one conductor element is formed through the filling material from top side to the back side for signal connection. A redistribution layer is formed on the at least one conductor element and coupled to die pad of the optical sensor element. A transparent material is formed on the redistribution layer.

Abstract translation: 本发明提供一种包括光学传感器元件的导体封装结构。 填充材料填充在光学传感器元件周围。 至少一个导体元件通过填充材料从顶侧到后面形成用于信号连接。 再分配层形成在至少一个导体元件上并且耦合到光学传感器元件的管芯焊盘。 在再分布层上形成透明材料。

公开(公告)号：US20110108977A1

公开(公告)日：2011-05-12

申请号：US12615682

申请日：2009-11-10

Applicant: Diann-Fang Lin ,  Yu-Shan Hu

Inventor： Diann-Fang Lin ,  Yu-Shan Hu

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract translation: 本发明公开了一种具有再分配层（RDL）和硅通孔（TSV）技术的半导体器件封装结构。 封装结构包括电子元件，该电子元件包括在电子元件的背面上的电介质层，穿过电子元件和电介质层的多个第一导电通孔以及伴随第一导电通孔的多个导电垫 在电子元件的有效表面上; 设置在电子元件附近的填充材料; 设置在电介质层和填充材料之上并连接到第一导电通孔的第一再分配层; 设置在电子元件的有源表面上的第一保护层，导电焊盘和填充材料; 以及设置在再分布层，电介质层和填充材料之上的第二保护层。

公开(公告)号：US07525185B2

公开(公告)日：2009-04-28

申请号：US11725827

申请日：2007-03-19

Applicant: Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

Inventor： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

IPC: H01L23/02

CPC classification number: H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.

Abstract translation: 本发明提供一种具有并排配置的多芯片的半导体器件封装，包括：具有通孔的基板，其中，所述基板具有通孔，连接通孔结构和上表面上的第一接触焊盘;以及第二接触焊盘， 基质。 具有第一接合焊盘的第一管芯和具有第二接合焊盘的第二管芯分别设置在管芯接收通孔内。 第一粘合材料形成在第一模具和第二模具和基板之下，并且第二粘合材料填充在第一和第二模具之间的间隙中以及接收基板的贯穿孔的模具的侧壁。 此外，形成接合线以在第二接合焊盘和第一接触焊盘之间在第一接合焊盘和第一接触焊盘之间耦合。 在接合线，第一和第二管芯和基板上形成介电层。 在基板的下表面和第一和第二模具的背面上形成堆积层。

公开(公告)号：US08749048B2

公开(公告)日：2014-06-10

申请号：US13091484

申请日：2011-04-21

Applicant: Diann-Fang Lin ,  Yu-Shan Hu

Inventor： Diann-Fang Lin ,  Yu-Shan Hu

IPC: H01L23/48

CPC classification number: H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract translation: 本发明公开了一种具有再分配层（RDL）和硅通孔（TSV）技术的半导体器件封装结构。 封装结构包括电子元件，该电子元件包括在电子元件的背面上的电介质层，穿过电子元件和电介质层的多个第一导电通孔，和与第一导电通孔 电子元件的活性表面上的通孔; 设置在电子元件附近的填充材料; 设置在电介质层和填充材料之上并连接到第一导电通孔的第一再分配层; 设置在电子元件的有源表面上的第一保护层，导电焊盘和填充材料; 以及设置在再分布层，电介质层和填充材料之上的第二保护层。

公开(公告)号：US20130065363A1

公开(公告)日：2013-03-14

申请号：US13327491

申请日：2011-12-15

Applicant: Diann-Fang Lin

Inventor： Diann-Fang Lin

IPC: H01L21/58 ,  H01L21/60

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48265 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.

Abstract translation: 公开了一种制造芯片封装结构的方法。 该制造方法包括以下步骤：提供保护层; 在保护层上形成导电迹线层; 在导电迹线层上形成粘附层; 将芯片放置在粘合层上; 并且将所述芯片电连接到所述导电迹线层。 通过这些布置，通过制造方法制造的芯片封装结构可以具有更小的厚度。

公开(公告)号：US07763494B2

公开(公告)日：2010-07-27

申请号：US12216658

申请日：2008-07-09

Applicant: Wen-Kun Yang ,  Diann-Fang Lin

Inventor： Wen-Kun Yang ,  Diann-Fang Lin

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29198 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/0715 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract translation: 本发明提供一种具有多芯片的半导体器件封装，该多芯片包括具有至少一个裸片接收通孔的基板，连接通孔结构和上表面上的第一接触焊盘以及在该基板的下表面上的第二接触焊盘。 至少具有第一接合焊盘的第一管芯设置在管芯接收通孔内。 第一粘合材料形成在模具下面，第二粘合材料填充在基板的模具和模具的侧壁之间的间隙中。 然后，形成第一接合线以耦合第一接合焊盘和第一接触焊盘。 此外，具有第二接合焊盘的至少第二管芯被放置在第一管芯上。 第二接合线被形成为耦合到第二接合焊盘和第一接触焊盘。 介电层形成在第一和第二接合线，第一和第二管芯和基底上。

公开(公告)号：US20080274593A1

公开(公告)日：2008-11-06

申请号：US12216658

申请日：2008-07-09

Applicant: Wen-Kun Yang ,  Diann-Fang Lin

Inventor： Wen-Kun Yang ,  Diann-Fang Lin

IPC: H01L21/58

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29198 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/0715 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract translation: 本发明提供一种具有多芯片的半导体器件封装，该多芯片包括具有至少一个裸片接收通孔的基板，连接通孔结构和上表面上的第一接触焊盘以及在该基板的下表面上的第二接触焊盘。 至少具有第一接合焊盘的第一管芯设置在管芯接收通孔内。 第一粘合材料形成在模具下面，第二粘合材料填充在基板的模具和模具的侧壁之间的间隙中。 然后，形成第一接合线以耦合第一接合焊盘和第一接触焊盘。 此外，具有第二接合焊盘的至少第二管芯被放置在第一管芯上。 第二接合线被形成为耦合到第二接合焊盘和第一接触焊盘。 介电层形成在第一和第二接合线，第一和第二管芯和基底上。

公开(公告)号：US20080230884A1

公开(公告)日：2008-09-25

申请号：US11725827

申请日：2007-03-19

Applicant: Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

Inventor： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/04 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.

Abstract translation: 本发明提供一种具有并排配置的多芯片的半导体器件封装，包括：具有通孔的基板，其中，所述基板具有通孔，连接通孔结构和上表面上的第一接触焊盘;以及第二接触焊盘， 基质。 具有第一接合焊盘的第一管芯和具有第二接合焊盘的第二管芯分别设置在管芯接收通孔内。 第一粘合材料形成在第一模具和第二模具和基板之下，并且第二粘合材料填充在第一和第二模具之间的间隙中以及接收基板的贯穿孔的模具的侧壁。 此外，形成接合线以在第二接合焊盘和第一接触焊盘之间在第一接合焊盘和第一接触焊盘之间耦合。 在接合线，第一和第二管芯和基板上形成介电层。 在基板的下表面和第一和第二模具的背面上形成堆积层。

公开(公告)号：US20050209805A1

公开(公告)日：2005-09-22

申请号：US10935084

申请日：2004-09-08

Applicant: Shih-Bou Chang ,  Diann-Fang Lin

Inventor： Shih-Bou Chang ,  Diann-Fang Lin

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  H01L21/00 ,  G06F19/00

CPC classification number: G01R31/318552 ,  G01R31/31922

Abstract: A method and system for generating test pulses to test electronic elements are disclosed. After determining a transmission clock, which is smaller than a test clock, and a serial of predetermined pulses, the serial of data bits corresponding to the serial of predetermined pulses can be generated. Then the serial of data bits can be transformed into a serial data stream for transmission. By transmitting the serial data stream according to the transmission clock, the serial of predetermined pulses corresponding to the test clock can be generated.

Abstract translation: 公开了一种用于产生测试电子元件测试脉冲的方法和系统。 在确定小于测试时钟的传输时钟和预定脉冲序列之后，可以产生与预定脉冲串相对应的数据位串。 然后将数据比特序列转换成串行数据流进行传输。 通过根据传输时钟发送串行数据流，可以产生与测试时钟对应的预定脉冲串。