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1.发明申请公开(公告)号：US20120228754A1
公开(公告)日：2012-09-13
申请号：US13415503
申请日：2012-03-08
申请人： FUHAN LIU , Venkatesh Sundaram , Nitesh Kumbhat , Rao Tummala
发明人： FUHAN LIU , Venkatesh Sundaram , Nitesh Kumbhat , Rao Tummala
IPC分类号： H01L25/07 , H01L23/495
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49833 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2225/06517 , H01L2225/06572 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/15153 , H01L2924/15311 , H01L2224/05599
摘要： The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
摘要翻译： 本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中IC嵌入在一至两个金属层基板内。 本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连， 用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘阵列（LGA）的降低的层数，以及改进的热管理选项。
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公开(公告)号：US08536695B2
公开(公告)日：2013-09-17
申请号：US13415503
申请日：2012-03-08
申请人： Fuhan Liu , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
发明人： Fuhan Liu , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
IPC分类号： H01L23/12 , H01L21/4763 , H05K1/00 , H05K1/03
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49833 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2225/06517 , H01L2225/06572 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/15153 , H01L2924/15311 , H01L2224/05599
摘要： The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
摘要翻译： 本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中IC嵌入在一至两个金属层基板内。 本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连， 用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘阵列（LGA）的降低的层数，以及改进的热管理选项。
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公开(公告)号：US09173282B2
公开(公告)日：2015-10-27
申请号：US13638536
申请日：2011-03-31
IPC分类号： H01R9/00 , H05K1/02 , H01L23/498 , H01L25/065 , H01R12/52 , H01R12/71 , H05K3/34 , H05K1/18 , H05K3/10 , H01L29/41 , H01L23/13 , H01L25/10 , H01L23/00
CPC分类号： H05K1/0213 , H01L23/13 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L29/413 , H01L2224/131 , H01L2224/16237 , H01L2224/45147 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81385 , H01L2224/81399 , H01L2224/81815 , H01L2224/8182 , H01L2224/8185 , H01L2224/81897 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1579 , H01L2924/15791 , H01R12/52 , H01R12/714 , H05K1/18 , H05K3/107 , H05K3/3436 , H05K2201/0248 , H05K2201/0281 , H05K2201/10378 , H05K2201/10674 , Y02P70/613 , H01L2924/014 , H01L2924/00 , H01L2224/48
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（μm）的间距。 互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。 每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。 本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。
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公开(公告)号：US20130107485A1
公开(公告)日：2013-05-02
申请号：US13638536
申请日：2011-03-31
CPC分类号： H05K1/0213 , H01L23/13 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L29/413 , H01L2224/131 , H01L2224/16237 , H01L2224/45147 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81385 , H01L2224/81399 , H01L2224/81815 , H01L2224/8182 , H01L2224/8185 , H01L2224/81897 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1579 , H01L2924/15791 , H01R12/52 , H01R12/714 , H05K1/18 , H05K3/107 , H05K3/3436 , H05K2201/0248 , H05K2201/0281 , H05K2201/10378 , H05K2201/10674 , Y02P70/613 , H01L2924/014 , H01L2924/00 , H01L2224/48
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。 互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。 每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。 本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。
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公开(公告)号：US20120104603A1
公开(公告)日：2012-05-03
申请号：US13383727
申请日：2010-07-13
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/81 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/75 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/16225 , H01L2224/32225 , H01L2224/731 , H01L2224/73204 , H01L2224/75 , H01L2224/75252 , H01L2224/75301 , H01L2224/81208 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15747 , H01L2924/15788 , H05K3/305 , H05K3/323 , H05K3/3436 , Y02P70/613 , H01L2924/00014 , H01L2924/00
摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
摘要翻译： 本发明的各种实施例提供细间距，芯片到衬底互连组件，以及制造和使用组件的方法。 组件通常包括具有管芯焊盘和设置在其上的凸块的半导体和其上设置有衬底焊盘的衬底。 凸起构造成当凸块与衬底焊盘接触时将半导体的至少一部分与衬底的至少一部分电互连。 此外，当凸块与衬底焊盘接触时，凸起的至少一部分和衬底焊盘的至少一部分变形，从而在它们之间产生非冶金结合。
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公开(公告)号：US08633601B2
公开(公告)日：2014-01-21
申请号：US13383727
申请日：2010-07-13
IPC分类号： H01L23/52
CPC分类号： H01L24/81 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/75 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/16225 , H01L2224/32225 , H01L2224/731 , H01L2224/73204 , H01L2224/75 , H01L2224/75252 , H01L2224/75301 , H01L2224/81208 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15747 , H01L2924/15788 , H05K3/305 , H05K3/323 , H05K3/3436 , Y02P70/613 , H01L2924/00014 , H01L2924/00
摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
摘要翻译： 本发明的各种实施例提供细间距，芯片到衬底互连组件，以及制造和使用组件的方法。 组件通常包括具有管芯焊盘和设置在其上的凸块的半导体和其上设置有衬底焊盘的衬底。 凸起构造成当凸块与衬底焊盘接触时将半导体的至少一部分与衬底的至少一部分电互连。 此外，当凸块与衬底焊盘接触时，凸起的至少一部分和衬底焊盘的至少一部分变形，从而在它们之间产生非冶金结合。
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公开(公告)号：US20130270695A1
公开(公告)日：2013-10-17
申请号：US13825815
申请日：2011-09-20
IPC分类号： H01L23/00
CPC分类号： H01L24/16 , H01L24/11 , H01L2224/16225 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K3/3436 , H05K3/4007 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。 所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中所述第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而提高所述两个电子部件之间的顺应性。 本发明的互连结构的多功能性，可扩展性和应力消除特性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。
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8.发明授权公开(公告)号：US08970036B2
公开(公告)日：2015-03-03
申请号：US13825815
申请日：2011-09-20
CPC分类号： H01L24/16 , H01L24/11 , H01L2224/16225 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K3/3436 , H05K3/4007 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
摘要翻译： 提供了一种应力消除的二级互连结构，其低成本并适应低TCE封装和印刷电路板（PCB）之间的热膨胀系数（TCE）不匹配。 所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而增强两个电子部件之间的顺应性。
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