利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

99 条记录 (耗时 0.022 秒)

    Preheating of chemical vapor deposition precursors
    1.
    发明申请
    Preheating of chemical vapor deposition precursors 审中-公开
    化学气相沉积前体预热

    公开(公告)号：US20050158997A1

    公开(公告)日：2005-07-21

    申请号：US11073798

    申请日：2005-03-07

    申请人： Garo Derderian ,  Gordon Morrison

    发明人： Garo Derderian ,  Gordon Morrison

    IPC分类号： C23C16/34 ,  C23C16/44 ,  C23C16/452 ,  C23C16/455 ,  C23C16/52 ,  H01L21/44

    CPC分类号： C23C16/4557 ,  C23C16/34 ,  C23C16/452 ,  C23C16/52 ,  H01L21/28556 ,  H01L21/76843

    摘要： Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which provides devices and systems with deposited layers substantially free of residual compounds from the reaction process. Heating reactant gases prior to introduction to a reaction chamber may be used to improve physical characteristics of the resulting deposited layer, to improve the physical characteristics of the underlying substrate and/or to improve the thermal budget available for subsequent processing. One example includes the formation of a titanium nitride layer substantially free of ammonium chloride using reactant gases containing a titanium tetrachloride precursor and a ammonia precursor.

    摘要翻译： 化学气相沉积系统包括在使气体反应以在基底上形成材料层之前预热反应气体的元件，其向装置和系统提供基本上没有来自反应过程的残余化合物的沉积层。 在引入反应室之前加热反应物气体可以用于改善所得沉积层的物理特性，以改善下面的基底的物理特性和/或改善可用于后续处理的热量预算。 一个实例包括使用含有四氯化钛前体和氨前体的反​​应气体形成基本上不含氯化铵的氮化钛层。

    Protection of tunnel dielectric using epitaxial silicon
    2.
    发明授权
    Protection of tunnel dielectric using epitaxial silicon 有权
    使用外延硅保护隧道电介质

    公开(公告)号：US07390710B2

    公开(公告)日：2008-06-24

    申请号：US10932795

    申请日：2004-09-02

    申请人： Garo Derderian ,  Nirmal Ramaswamy

    发明人： Garo Derderian ,  Nirmal Ramaswamy

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336

    摘要： Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

    摘要翻译： 使用外延硅层来保护浮栅存储器单元的隧道介电层免于在形成浅沟槽隔离（STI）区域期间的过度氧化或去除。 在沟槽形成之后，外延硅层从隧道介电层的相对侧上的含硅层生长，从而允许其厚度被限制为隧道介电层的厚度的大约二分之一。 外延硅可以在用电介质材料填充沟槽之前被氧化，或者在氧化至少覆盖隧道介电层的端部的外延硅之前可能发生电介质填充。

    MIS capacitor and method of formation
    5.
    发明申请
    MIS capacitor and method of formation 有权
    MIS电容器和形成方法

    公开(公告)号：US20070138529A1

    公开(公告)日：2007-06-21

    申请号：US11545481

    申请日：2006-10-11

    申请人： Cem Basceri ,  Garo Derderian

    发明人： Cem Basceri ,  Garo Derderian

    IPC分类号： H01L29/94

    CPC分类号： H01L28/40 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/84 ,  H01L28/91 ,  H01L29/94

    摘要： An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

    摘要翻译： 公开了具有低泄漏和高电容的MIS电容器。 形成半球状晶粒多晶硅层（HSG）作为下电极。 在电介质形成之前，半球状晶粒多晶硅层可以任选地进行氮化或退火工艺。 在半球形颗粒上制造氧化铝（Al 2 O 3 3）的介电层或氧化铝和其它金属氧化物电介质材料的交错层的复合叠层 多晶硅层和可选的氮化或退火工艺后。 氧化铝（Al 2 O 3 3）的电介质层或氧化铝复合叠层可以任选地进行后沉积处理以进一步增加电容并减小 漏电流。 通过沉积技术或通过原子层沉积在电介质层或复合叠层上形成金属氮化物上电极。

    NAND memory arrays
    6.
    发明申请
    NAND memory arrays 审中-公开
    NAND存储器阵列

    公开(公告)号：US20070063262A1

    公开(公告)日：2007-03-22

    申请号：US11601095

    申请日：2006-11-17

    申请人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    发明人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S438/981

    摘要： A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.

    摘要翻译： NAND存储器阵列具有多行存储器单元和多列存储器单元的NAND串。 每个NAND串通过相应列的漏极选择栅选择性地连接到位线。 每个漏极选择栅极具有形成在存储器阵列的半导体衬底上的第一电介质层和形成在第一介电层上的控制栅极。 每个NAND串的每个存储单元具有形成在与第一介电层相邻的基板上的第二介质层，形成在第二介电层上的浮动栅极，形成在浮置栅极上的第三介电层，以及控制栅极 形成在第三电介质层上。 第一电介质层比第二电介质层厚。

    Atomic layer deposition method of depositing an oxide on a substrate
    7.
    发明申请
    Atomic layer deposition method of depositing an oxide on a substrate 有权
    在衬底上沉积氧化物的原子层沉积方法

    公开(公告)号：US20060257584A1

    公开(公告)日：2006-11-16

    申请号：US11491383

    申请日：2006-07-20

    申请人： Garo Derderian ,  Shuang Meng ,  Danny Dynka

    发明人： Garo Derderian ,  Shuang Meng ,  Danny Dynka

    IPC分类号： H05H1/24 ,  C23C16/00

    CPC分类号： C23C16/45542 ,  C23C16/402 ,  C23C16/403 ,  C23C16/407 ,  C23C16/45531

    摘要： The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed onto the substrate to form a first species monolayer within the deposition chamber from a gaseous precursor. The chemisorbed first species is contacted with remote plasma oxygen derived at least in part from at least one of O2 and O3 and with remote plasma nitrogen effective to react with the first species to form a monolayer comprising an oxide of a component of the first species monolayer. The chemisorbing and the contacting with remote plasma oxygen and with remote plasma nitrogen are successively repeated effective to form porous oxide on the substrate. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括在衬底上沉积氧化物的原子层沉积方法。 在一个实施方式中，衬底位于沉积室内。 第一种物质被化学吸附到基底上以在气相前体的沉积室内形成第一物质单层。 化学吸附的第一物质与至少部分从O 2和O 3 3中的至少一个导出的远程等离子体氧接触，并且与远程等离子体氮有效地与第一物质反应 物质形成包含第一物质单层的组分的氧化物的单层。 连续重复化学吸附和与远程等离子体氧和远程等离子体氮的接触，以在衬底上形成多孔氧化物。 考虑了其他方面和实现。

    Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
    8.
    发明申请
    Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry 失效

    公开(公告)号：US20060183347A1

    公开(公告)日：2006-08-17

    申请号：US11404541

    申请日：2006-04-14

    申请人： Garo Derderian ,  Chris Hill

    发明人： Garo Derderian ,  Chris Hill

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02164 ,  C23C16/0272 ,  C23C16/402 ,  H01L21/02145 ,  H01L21/02214 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76227

    摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.

    Methods of forming trench isolation regions
    10.
    发明申请
    Methods of forming trench isolation regions 有权
    形成沟槽隔离区的方法

    公开(公告)号：US20060003544A1

    公开(公告)日：2006-01-05

    申请号：US11209081

    申请日：2005-08-22

    申请人： Garo Derderian ,  H. Manning

    发明人： Garo Derderian ,  H. Manning

    IPC分类号： H01L21/76 ,  H01L21/302

    CPC分类号： H01L21/76224

    摘要： The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.

    摘要翻译： 本发明包括形成沟槽隔离区域的方法。 在一个实施方式中，在半导体衬底上形成掩模材料。 掩模材料包括钨，氮化钛和无定形碳中的至少一种。 通过掩模材料和半导体衬底形成有效地在半导体衬底的半导体材料内形成隔离沟槽的开口。 沟槽隔离材料形成在隔离沟槽内并且在沟槽外部的掩模材料之上，有效地覆盖隔离沟槽。 沟槽隔离材料至少抛光到掩模材料的钨，氮化钛和无定形碳中的至少一种的最外表面。 从衬底蚀刻钨，氮化钛和无定形碳中的至少一种。 考虑其他实现和方面。