公开(公告)号：US08140297B2

公开(公告)日：2012-03-20

申请号：US12354958

申请日：2009-01-16

申请人： Gerald K. Bartley ,  Charles L. Johnson ,  Mark M. Thornton ,  Patrick R. Varekamp

发明人： Gerald K. Bartley ,  Charles L. Johnson ,  Mark M. Thornton ,  Patrick R. Varekamp

IPC分类号： G06F11/22 ,  G06F11/00 ,  G06F11/30 ,  G01R31/26 ,  G01R31/00 ,  G01R31/02 ,  G01D21/00

CPC分类号： G06F19/00 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip. The components from the 2D chip are layered and coupled to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

摘要翻译： 三维（3D）芯片由已经从二维（2D）芯片切出的部件制成。 来自2D芯片的组件被分层和耦合以产生3D芯片的层。 首先通过测试2D芯片，3D芯片的层已经过预先测试，从而降低了测试和生产成本。

公开(公告)号：US20120038057A1

公开(公告)日：2012-02-16

申请号：US12855854

申请日：2010-08-13

申请人： Gerald K. Bartley ,  Russell D. Hoover ,  Charles L. Johnson ,  Steven P. VanderWiel

发明人： Gerald K. Bartley ,  Russell D. Hoover ,  Charles L. Johnson ,  Steven P. VanderWiel

IPC分类号： H01L23/538 ,  G06F17/50 ,  H01L21/50

CPC分类号： H01L23/50 ,  G06F17/5068 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L2224/06519 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

摘要翻译： 一个方面的电路装置和方法利用仅在通孔之间通过在堆叠的半导体管芯的相对表面之间延伸的热，以增加多层半导体堆叠的导热性。 除了通过通孔之类的数据传送之外，提供了热通孔，该通路通过电路层之间传送数据信号，并通过通孔进行通电，通孔与耦合到电路层的配电网络，使得热导率增加到 可以通过堆叠中的通孔的数据携带和供电来提供。 另一方面的电路装置和方法基于电流密度组织多层半导体堆叠中的电路层，以便减少堆叠中的功率分配损失。

公开(公告)号：US20140070393A1

公开(公告)日：2014-03-13

申请号：US13613564

申请日：2012-09-13

申请人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

发明人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC分类号： H01L23/367 ,  H01L21/02 ,  H01L23/00

CPC分类号： H01L23/367 ,  H01L21/02656 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4275 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83909 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

摘要： The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip

摘要翻译： 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维，并且纳米纤维垂直于第一芯片和第二芯片的配合表面对齐 芯片和第二芯片

公开(公告)号：US08367478B2

公开(公告)日：2013-02-05

申请号：US13151672

申请日：2011-06-02

申请人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

发明人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  David R. Motschman

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L23/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/538

CPC分类号： H01L29/0657 ,  H01L23/3677 ,  H01L23/4275 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

摘要： The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

摘要翻译： 本发明的示例性实施例提供了一种用于增强半导体芯片的芯片堆叠的冷却的方法和装置。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在连接器之间的第一芯片的第二侧中形成空腔，并用热材料填充空腔。 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括：其中，连接器之间的第一芯片的第二侧的部分被去除以提供放置热材料的空腔。

公开(公告)号：US09111899B2

公开(公告)日：2015-08-18

申请号：US13613564

申请日：2012-09-13

申请人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

发明人： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC分类号： H01L23/48 ,  H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L23/00 ,  H01L21/02 ,  H01L23/373 ,  H01L23/427 ,  H01L25/065

CPC分类号： H01L23/367 ,  H01L21/02656 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4275 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83909 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

摘要： The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.

摘要翻译： 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维，并且纳米纤维垂直于第一芯片和第二芯片的配合表面对齐 芯片和第二芯片。

公开(公告)号：US09495498B2

公开(公告)日：2016-11-15

申请号：US13618600

申请日：2012-09-14

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

IPC分类号： H01L25/00 ,  G06F17/50 ,  H01L25/065

CPC分类号： G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

摘要翻译： 一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

公开(公告)号：US20130277798A1

公开(公告)日：2013-10-24

申请号：US13449480

申请日：2012-04-18

申请人： Gerald K. Bartley ,  Philip R. Germann ,  John E. Sheets, II

发明人： Gerald K. Bartley ,  Philip R. Germann ,  John E. Sheets, II

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.

摘要翻译： 提供了一种用于实现具有深沟槽和透硅（Via-Silicon-Via，TSV）技术的具有半导体信号能力的电容器的方法和结构。 形成深沟槽N阱结构，并且在深沟槽N阱结构中提供植入物，其中TSV形成在半导体芯片中。 在半导体芯片中的TSV周围形成至少一个成角度的植入物。 TSV被介电层包围并填充有形成电容器的一个电极的导电材料。 连接到形成到电容器的第二电极的一个注入件。

公开(公告)号：US08445918B2

公开(公告)日：2013-05-21

申请号：US12855854

申请日：2010-08-13

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC分类号： H01L31/0312

CPC分类号： H01L23/50 ,  G06F17/5068 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L2224/06519 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

摘要翻译： 一个方面的电路装置和方法利用仅在通孔之间通过在堆叠的半导体管芯的相对表面之间延伸的热，以增加多层半导体堆叠的导热性。 除了通过通孔之类的数据传送之外，提供了热通孔，该通路通过电路层之间传送数据信号，并通过通孔进行通电，通孔与耦合到电路层的配电网络，使得热导率增加到 可以通过堆叠中的通孔的数据携带和供电来提供。 另一方面的电路装置和方法基于电流密度组织多层半导体堆叠中的电路层，以便减少堆叠中的功率分配损失。

公开(公告)号：US20130011968A1

公开(公告)日：2013-01-10

申请号：US13618656

申请日：2012-09-14

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

摘要翻译： 电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件 使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。 通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和 功能。

公开(公告)号：US20120098140A1

公开(公告)日：2012-04-26

申请号：US12911879

申请日：2010-10-26

申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC分类号： H01L23/538 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

摘要翻译： 电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件 使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。 通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和 功能。