公开(公告)号：US6064082A

公开(公告)日：2000-05-16

申请号：US86988

申请日：1998-05-29

申请人： Hiroji Kawai ,  Shunji Imanaga ,  Toshimasa Kobayashi

发明人： Hiroji Kawai ,  Shunji Imanaga ,  Toshimasa Kobayashi

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/20 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L35/26

CPC分类号： H01L29/7783 ,  H01L29/2003

摘要： A heterojunction field effect transistor realizing a high performance by a significant decrease. in source resistance while maintaining a sufficiently high gate resistivity to voltage is provided. Sequentially stacked on a c-face sapphire substrate via a buffer layer are an undoped GaN layer, undoped Al.sub.0.3 Ga.sub.07 N layer, undoped GaN channel layer, undoped Al.sub.0.15 Ga.sub.0.85 N spacer layer, n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer, graded undoped Al.sub.z Ga.sub.1-z N barrier layer and n-type Al.sub.0.06 Ga.sub.0.94 N contact layer, and a gate electrode, source electrode and drain electrode are formed on the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer to form a AlGaN/GaN HEMT. The Al composition z in the graded undoped Al.sub.z Ga.sub.1-z N barrier layer continuously decreases from 0.15 to 0.06, for example, from the n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer toward the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer. An n.sup.++ -type GaN contact layer may be formed on the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer in the region for the source electrode and the drain electrode, and the source electrode and the drain may be formed on it.

摘要翻译： 异质结场效应晶体管通过显着降低实现高性能。 提供了源电阻，同时保持足够高的栅极电阻率对电压。 经缓冲层顺序堆叠在c面蓝宝石衬底上的是未掺杂的GaN层，未掺杂的Al0.3Ga07N层，未掺杂的GaN沟道层，未掺杂的Al 0.15 Ga 0.85嵌入层，n型Al 0.15 Ga 0.85纳米电子供体层 渐变未掺杂的AlzGa1-zN势垒层和n型Al0.06Ga0.94N接触层，在n型Al0.06Ga0.94N接触层上形成栅电极，源电极和漏电极，形成AlGaN / GaN HEMT。 渐变非掺杂AlzGa1-zN阻挡层中的Al组分z例如从n型Al 0.15 Ga 0.85 N电子供给层向n型Al0.06Ga0.94N接触层连续地从0.15减少到0.06。 可以在用于源电极和漏电极的区域中的n型Al0.06Ga0.94N接触层上形成n ++型GaN接触层，并且可以在其上形成源电极和漏极。

公开(公告)号：US6140169A

公开(公告)日：2000-10-31

申请号：US283696

申请日：1999-04-01

申请人： Hiroji Kawai ,  Shunji Imanaga

发明人： Hiroji Kawai ,  Shunji Imanaga

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/335 ,  H01L21/336 ,  H01L29/20 ,  H01L29/51 ,  H01L29/778 ,  H01L29/78

CPC分类号： H01L29/518 ,  H01L21/28194 ,  H01L21/28587 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/2003

摘要： A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.

摘要翻译： 通过使用栅极绝缘膜，GaN型场效应晶体管呈现大的输入振幅。 沟道层和栅极绝缘膜依次层压在其间具有缓冲层的基板上。 在栅极绝缘膜上形成栅电极。 源电极和漏极设置在栅电极的两侧，并且经由开口电连接到沟道层。 沟道层由n型GaN形成。 栅绝缘膜由AlN制成，其表现出优异的绝缘特性，从而增加肖特基势垒并实现大的输入幅度。 如果FET在增强模式下工作，则其可以以类似于Si-MOS型FET的方式工作，导致反型层的形成。

公开(公告)号：US5929467A

公开(公告)日：1999-07-27

申请号：US984635

申请日：1997-12-03

申请人： Hiroji Kawai ,  Shunji Imanaga

发明人： Hiroji Kawai ,  Shunji Imanaga

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/335 ,  H01L21/336 ,  H01L29/20 ,  H01L29/51 ,  H01L29/778 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/518 ,  H01L21/28194 ,  H01L21/28587 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/2003

摘要： A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.

摘要翻译： 通过使用栅极绝缘膜，GaN型场效应晶体管呈现大的输入振幅。 沟道层和栅极绝缘膜依次层压在其间具有缓冲层的基板上。 在栅极绝缘膜上形成栅电极。 源电极和漏极设置在栅电极的两侧，并且经由开口电连接到沟道层。 沟道层由n型GaN形成。 栅绝缘膜由AlN制成，其表现出优异的绝缘特性，从而增加肖特基势垒并实现大的输入幅度。 如果FET在增强模式下工作，则其可以以类似于Si-MOS型FET的方式操作，导致反型层的形成。

公开(公告)号：US4758870A

公开(公告)日：1988-07-19

申请号：US713636

申请日：1985-03-19

申请人： Ichiro Hase ,  Hiroji Kawai ,  Shunji Imanaga ,  Kunio Kaneko

发明人： Ichiro Hase ,  Hiroji Kawai ,  Shunji Imanaga ,  Kunio Kaneko

IPC分类号： H01L29/20 ,  H01L29/205 ,  H01L29/68 ,  H01L29/76 ,  H01L29/72

CPC分类号： H01L29/205 ,  H01L29/7606

摘要： A III-V semiconductor device is disclosed, which includes an emitter region, an emitter barrier region having such a barrier height as to substantially restrict a thermionic emission current as compared with a tunneling current and such a barrier width as to permit the tunneling current, a base region containing indium and having higher electron affinity than said emitter region and a collector barrier region having such a barrier height as to substantially prohibit a thermally distributed electron from overflowing and such a barrier width as to substantially prohibit the tunneling current.

摘要翻译： 公开了一种III-V半导体器件，其包括发射极区域，具有这样的势垒高度的发射极阻挡区域，其与隧道电流相比基本上限制热离子发​​射电流，并且具有允许隧穿电流的这种势垒宽度， 包含铟并且具有比所述发射极区域更高的电子亲和力的基极区域和具有这样的势垒高度的集电极势垒区域，以便基本上禁止热分布电子溢出，并且这种势垒宽度基本上禁止隧穿电流。

公开(公告)号：US06281032B1

公开(公告)日：2001-08-28

申请号：US09291016

申请日：1999-04-14

申请人： Osamu Matsuda ,  Toshimasa Kobayashi ,  Norikazu Nakayama ,  Hiroji Kawai

发明人： Osamu Matsuda ,  Toshimasa Kobayashi ,  Norikazu Nakayama ,  Hiroji Kawai

IPC分类号： H01L2100

CPC分类号： H01S5/34333 ,  B82Y20/00 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/8252 ,  H01L33/0079 ,  H01L2221/68363 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01S5/0202 ,  H01S5/021 ,  H01S5/0213 ,  H01S5/0215 ,  H01S5/0217 ,  H01S5/02212 ,  H01S5/0264 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a semiconductor device manufacturing method capable of manufacturing semiconductor lasers, light emitting diodes or electron transport devices using nitride III-V compound semiconductors with a high productivity, a GaN semiconductor laser wafer is prepared in which a plurality of semiconductor lasers are formed on an AlGaInN semiconductor layer on a c-face sapphire substrate and separated from each other by grooves deep enough to reach the c-face sapphire substrate, and a p-side electrode and an n-side electrode are formed in each semiconductor laser. The GaN semiconductor laser wafer is bonded to a photo-diode built-in Si wafer having formed a photo diode for monitoring light outputs and solder electrodes in each pellet by positioning the p-side electrode and the n-side electrode in alignment with the solder electrodes, respectively. After that, by lapping the c-face sapphire substrate from its bottom surface deep enough to reach the grooves or by dicing the c-face sapphire substrate from its bottom surface, the semiconductor lasers on the photo-diode built-in Si wafer are separated from each other. After that, the photo-diode built-in Si wafer is divided by dicing into discrete pellets. A GaN semiconductor laser chip, thus obtained, is assembled on a package.

摘要翻译： 在能够以高生产率制造半导体激光器，发光二极管或使用氮化物III-V化合物半导体的电子传输装置的半导体器件制造方法中，制备GaN半导体激光晶片，其中在AlGaInN上形成多个半导体激光器 半导体层，并且通过深度足以到达c面蓝宝石衬底的沟槽彼此分离，并且在每个半导体激光器中形成p侧电极和n侧电极。 将GaN半导体激光晶片通过将p侧电极和n侧电极定位在与焊料对准的状态下，与形成有二极管的光电二极管内置Si晶片接合，该光电二极管用于监测各个芯片中的光输出和焊料电极 电极。 之后，通过将C面蓝宝石衬底从其底部表面深度研磨到达凹槽或通过从其底部表面切割c面蓝宝石衬底，将二极管内置硅晶片上的半导体激光器分离 从彼此。 之后，光电二极管内置硅晶片通过切割分割成分散的颗粒。 由此获得的GaN半导体激光芯片组装在封装上。

公开(公告)号：US20130126942A1

公开(公告)日：2013-05-23

申请号：US13639075

申请日：2011-06-21

申请人： Akira Nakajima ,  Sankara Narayanan Ekkanath Madathil ,  Yasunobu Sumida ,  Hiroji Kawai

发明人： Akira Nakajima ,  Sankara Narayanan Ekkanath Madathil ,  Yasunobu Sumida ,  Hiroji Kawai

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0619 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66219 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L29/872

摘要： A low-loss GaN-based semiconductor device is provided.The semiconductor device has the InzGa1-zN layer (where 0≦z

摘要翻译： 提供了一种低损耗GaN基半导体器件。 半导体器件具有InzGa1-zN层（其中0 @ z <1），Al x Ga 1-x N层（其中0

公开(公告)号：US20120280363A1

公开(公告)日：2012-11-08

申请号：US13389385

申请日：2010-08-17

申请人： Yasunobu Sumida ,  Shoko Hirata ,  Takayuki Inada ,  Shuichi Yagi ,  Hiroji Kawai

发明人： Yasunobu Sumida ,  Shoko Hirata ,  Takayuki Inada ,  Shuichi Yagi ,  Hiroji Kawai

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： C30B29/406 ,  C30B25/04 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/66446

摘要： The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.

摘要翻译： 制造半导体器件的方法包括以下步骤：在包括不同于GaN基半导体的材料的衬底上直接或间接地形成具有多个开口的生长掩模; 以及使用所述生长掩模在（0001）面取向中在所述基板上生长多个岛状GaN基半导体层，使得所述1-100方向在与生长掩模的条纹开口平行的方向上延伸 。

公开(公告)号：USRE38613E1

公开(公告)日：2004-10-05

申请号：US10174289

申请日：2002-09-18

申请人： Hiroji Kawai ,  Tsunenori Asatsuma ,  Fumihiko Nakamura

发明人： Hiroji Kawai ,  Tsunenori Asatsuma ,  Fumihiko Nakamura

IPC分类号： H01L2104

CPC分类号： H01L33/325 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262

摘要： A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment, a p-type nitride compound semiconductor, such as p-type GaN, is grown by metal organic chemical vapor deposition methods using a nitrogen source material which does not release hydrogen during release of nitrogen and the semiconductor is grown in an inactive gas. The nitrogen source materials may be selected from nitrogen compounds that contain hydrogen radicals groups and alkyl radicals groups and/or phenyl radicals groups provided that the total amount of hydrogen radicals groups is less than or equal to the sum total of alkyl radicals groups and phenyl radicals groups present in the nitrogen compound used as the nitrogen source material.

公开(公告)号：US06235617B1

公开(公告)日：2001-05-22

申请号：US09588410

申请日：2000-06-06

申请人： Hiroji Kawai

发明人： Hiroji Kawai

IPC分类号： H01L218242

CPC分类号： H01L29/66212 ,  H01L21/2654 ,  H01L21/7605 ,  H01L21/8252 ,  H01L21/86 ,  H01L29/475 ,  H01L29/66863 ,  H01L29/812 ,  H01S5/20 ,  H01S5/2059 ,  H01S5/2231 ,  H01S5/32341

摘要： It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation. After a nitride III-V compound semiconductor layer having an electric conductivity is grown, a high resistance region is formed in the nitride III-V compound semiconductor layer by locally implanting boron ions therein. The amount of implanted boron is preferably not less than {fraction (1/30)}, or more preferably not less than {fraction (1/15)}, of the carrier concentration of the nitride III-V compound semiconductor layer. The high-resistance region is used as a device isolating region of an electron moving device or as a current blocking layer of a semiconductor laser.

摘要翻译： 旨在提供一种半导体器件及其制造方法，其中即使在高温下仍能保持高电阻的高电阻区域可以通过离子注入在具有导电性的氮化物III-V化合物半导体层中进行。 在生长具有导电性的氮化物III-V化合物半导体层之后，通过在其中局部注入硼离子，在氮化物III-V化合物半导体层中形成高电阻区域。 注入硼的量优选不小于氮化物III-V化合物半导体层的载流子浓度的{分数（1/30）}，更优选不小于{分数（1/15）}。 高电阻区域用作电子移动器件的器件隔离区域或半导体激光器的电流阻挡层。

公开(公告)号：US5753966A

公开(公告)日：1998-05-19

申请号：US772066

申请日：1996-12-19

申请人： Etsuo Morita ,  Hiroji Kawai

发明人： Etsuo Morita ,  Hiroji Kawai

IPC分类号： H01S5/02 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01S5/0201 ,  H01S5/0202

摘要： A semiconductor light emitting device is prepared by the steps of forming a semiconductor layer 2 having a laminated structure containing at least a first cladding layer 6, a light emitting layer 7, and a second cladding layer 8 on a substrate 1 having {11-20} plane (plane a) as the main plane; and breaking integrally the semiconductor layer 2 and the substrate 1 under a heating condition to form a pair of facets on the above described substrate due to the plane which was cleaved in {1-102} plane (plane r) and at the same time, to form a pair of facets 3 extending along the above described pair of facets of the substrate 1 on the semiconductor layer 2.

摘要翻译： 通过以下步骤制备半导体发光器件：具有至少包含第一覆层6，发光层7和第二覆层8的层叠结构的半导体层2，具有{11-20 }面（平面a）为主面; 并且在加热条件下将半导体层2和基板1整体断开，由于在{1-102}面（平面r）中被切割的平面而在上述基板上形成一对面，同时， 以形成沿着半导体层2上的衬底1的上述一对面延伸的一对面3。