公开(公告)号：US6121636A

公开(公告)日：2000-09-19

申请号：US72177

申请日：1998-05-05

申请人： Etsuo Morita ,  Hiroji Kawai

发明人： Etsuo Morita ,  Hiroji Kawai

IPC分类号： H01L33/32 ,  H01L33/40 ,  H01L33/46 ,  H01L33/54 ,  H01L33/56 ,  H01L33/62 ,  H01S5/00 ,  H01S5/323 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L33/20 ,  H01L33/32 ,  H01L33/46 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49107 ,  H01L2224/73265

摘要： A semiconductor light emitting device is provided, which does not deteriorate in luminance, maintains a high reliability, permits more free choice of an adhesive, and promises effective extraction of light to the exterior even when it is bonded to a lead frame or other support with the adhesive in practical use. In a GaN light emitting diode, GaN compound semiconductor layers are stacked sequentially on a front surface of a sapphire substrate to form a light emitting diode structure, and a reflective film is formed on a rear surface. Alternatively, the GaN compound semiconductor layers forming the light emitting diode structure are selectively removed by etching to define an inverted mesa-shaped end surface, and the reflective film is formed on the end surface. Both the p-side electrode and the n-side electrode are formed on a common side of the substrate where the GaN compound semiconductor layers are formed.

摘要翻译： 提供一种半导体发光器件，其不会劣化亮度，保持高可靠性，允许更自由地选择粘合剂，并且即使当将其粘合到引线框架或其他支撑件上时也能有效地将光提取到外部， 粘合剂在实际使用中。 在GaN发光二极管中，GaN化合物半导体层依次层叠在蓝宝石衬底的前表面上以形成发光二极管结构，并且在后表面上形成反射膜。 或者，通过蚀刻选择性地除去形成发光二极管结构的GaN化合物半导体层，以限定倒置的台面状端面，并且在端面上形成反射膜。 p侧电极和n侧电极都形成在形成GaN化合物半导体层的基板的共同侧。

公开(公告)号：US6107162A

公开(公告)日：2000-08-22

申请号：US59827

申请日：1998-04-14

申请人： Etsuo Morita ,  Hiroji Kawai

发明人： Etsuo Morita ,  Hiroji Kawai

IPC分类号： H01L21/20 ,  H01L33/14 ,  H01L33/16 ,  H01L33/20 ,  H01L33/32 ,  H01S5/00 ,  H01S5/02 ,  H01S5/042 ,  H01S5/10 ,  H01S5/323 ,  H01L21/46

CPC分类号： H01S5/0201 ,  H01S5/0422 ,  H01S5/0202 ,  H01S5/0213 ,  H01S5/1082 ,  H01S5/32341

摘要： A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the substrate or the substrate easily succumbs to cleavage, then the semiconductor layer together with the substrate can be broken into chips in an easy-to-cleave plane. The cleaved surface of the semiconductor layer can be positively formed as an optically superior surface. A compound semiconductor layer 2 containing at least one of the elements {Ga, Al, In} and N is formed on the substrate 1. This compound semiconductor layer 2 has a pair of facets of {11-20} plane substantially perpendicular to the substrate 1.

摘要翻译： 诸如半导体层的半导体器件由诸如GaN的III-V族的化合物半导体层形成。 在衬底没有任何容易切割的平面与衬底上生长的半导体层的容易解理平面或衬底容易陷入裂纹的情况相一致的情况下，半导体层与衬底一起可以 在易于分裂的飞机上被破碎成碎片。 可以将半导体层的分解面牢固地形成为光学优良的表面。 包含至少一种元素{Ga，Al，In}和N的化合物半导体层2形成在基板1上。该化合物半导体层2具有与基板垂直的{11-20}面的一对面 1。

公开(公告)号：US20080050599A1

公开(公告)日：2008-02-28

申请号：US11976246

申请日：2007-10-23

申请人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

发明人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

IPC分类号： B32B9/04

CPC分类号： H01L21/02538 ,  C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265

摘要： A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces (13a), (13b) in an end of each threading dislocation D1 elongating from below. The threading dislocation D1 is separated from the upper layer by the spaces (13a), (13b), so that each threading dislocation D1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D1 expressed by Burgers vector is preserved to develop another dislocation, the spaces (13a), (13b) vary the direction of its displacement. As a result, the upper layer above the spaces (13a), (13b) turns crystalline with a low dislocation density.

公开(公告)号：US5828086A

公开(公告)日：1998-10-27

申请号：US826108

申请日：1997-03-24

申请人： Akira Ishibashi ,  Satoshi Matsumoto ,  Masaharu Nagai ,  Satoshi Ito ,  Shigetaka Tomiya ,  Kazushi Nakano ,  Etsuo Morita

发明人： Akira Ishibashi ,  Satoshi Matsumoto ,  Masaharu Nagai ,  Satoshi Ito ,  Shigetaka Tomiya ,  Kazushi Nakano ,  Etsuo Morita

IPC分类号： H01L33/06 ,  H01L33/28 ,  H01S5/30 ,  H01S5/32 ,  H01S5/347 ,  H01L33/00

CPC分类号： H01L33/28 ,  B82Y20/00 ,  H01L33/06 ,  H01S5/347 ,  H01S2304/02 ,  H01S5/3059 ,  H01S5/3216

摘要： A semiconductor light emitting device ccomprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still anothr semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, a first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.

摘要翻译： 半导体发光器件包括堆叠在半导体衬底上的第一覆层，有源层和第二覆层。 第一包层和第二包层的至少一部分具有包含II-VI化合物半导体的超晶格结构。 另一种半导体发光器件包括堆叠在半导体衬底上的第一覆层，第一引导层，有源层，第二引导层和第二覆层。 第一包覆层，第一引导层，第二覆盖层和第二引导层的至少一部分具有超晶格结构。 还有一种半导体发光器件包括堆叠在半导体衬底上的缺陷分解层，缺陷阻挡层，第一覆层，有源层，第二覆层。 缺陷分解层和缺陷阻挡层包括超晶格结构。

公开(公告)号：US5705421A

公开(公告)日：1998-01-06

申请号：US561865

申请日：1995-11-22

申请人： Takeshi Matsushita ,  Etsuo Morita ,  Tsuneo Nakajima ,  Hiroyuki Hasegawa ,  Takayuki Shingyouji

发明人： Takeshi Matsushita ,  Etsuo Morita ,  Tsuneo Nakajima ,  Hiroyuki Hasegawa ,  Takayuki Shingyouji

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S438/97 ,  Y10S438/977

摘要： A SOI substrate fabricating method comprises the steps of: making a first etch-stop layer on a silicon substrate; polishing the surface of the first etch-stop layer; making a silicon buffer layer on the polished surface of the first etch-stop layer; making a silicon layer on the silicon buffer layer; making an insulating layer on the silicon layer; bonding one of major surfaces of a support substrate onto the insulating layer; and removing the silicon substrate, the first etch-stop layer and the silicon buffer layer and maintaining the insulating layer and the silicon layer on the one surface of the support substrate. Another SOI substrate fabricating method comprising the steps of: making a first etch-stop layer on a silicon substrate; polishing one surface of the first etch-stop layer; making a silicon buffer layer on the polished surface of the first etch-stop layer; making a compound semiconductor layer comprising silicon and at least one of germanium and carbon on the silicon buffer layer; making an insulating layer on the compound semiconductor layer; bonding one of major surfaces of a support substrate onto the insulating layer; and removing the silicon substrate, the first etch-stop layer and the silicon buffer layer and maintaining the insulating layer and the compound semiconductor layer on the one surface of the support substrate.

摘要翻译： SOI衬底制造方法包括以下步骤：在硅衬底上制造第一蚀刻停止层; 抛光第一蚀刻停止层的表面; 在第一蚀刻停止层的抛光表面上制造硅缓冲层; 在硅缓冲层上形成硅层; 在硅层上形成绝缘层; 将支撑基板的主表面之一粘合到绝缘层上; 以及去除硅衬底，第一蚀刻停止层和硅缓冲层，并且将绝缘层和硅层保持在支撑衬底的一个表面上。 另一种SOI衬底制造方法包括以下步骤：在硅衬底上制造第一蚀刻停止层; 抛光第一蚀刻停止层的一个表面; 在第一蚀刻停止层的抛光表面上制造硅缓冲层; 在硅缓冲层上制造包含硅和锗和碳中的至少一种的化合物半导体层; 在化合物半导体层上形成绝缘层; 将支撑基板的主表面之一粘合到绝缘层上; 以及去除硅衬底，第一蚀刻停止层和硅缓冲层，并将绝缘层和化合物半导体层保持在支撑衬底的一个表面上。

公开(公告)号：US5665977A

公开(公告)日：1997-09-09

申请号：US691536

申请日：1996-08-02

申请人： Akira Ishibashi ,  Satoshi Matsumoto ,  Masaharu Nagai ,  Satoshi Ito ,  Shigetaka Tomiya ,  Kazushi Nakano ,  Etsuo Morita

发明人： Akira Ishibashi ,  Satoshi Matsumoto ,  Masaharu Nagai ,  Satoshi Ito ,  Shigetaka Tomiya ,  Kazushi Nakano ,  Etsuo Morita

IPC分类号： H01L33/06 ,  H01L33/28 ,  H01S5/30 ,  H01S5/32 ,  H01S5/347 ,  H01L33/00

CPC分类号： H01L33/28 ,  B82Y20/00 ,  H01L33/06 ,  H01S5/347 ,  H01S2304/02 ,  H01S5/3059 ,  H01S5/3216

摘要： A semiconductor light emitting device comprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still another semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.

摘要翻译： 半导体发光器件包括堆叠在半导体衬底上的第一覆层，有源层和第二覆层。 第一包层和第二包层的至少一部分具有包含II-VI化合物半导体的超晶格结构。 另一半导体发光器件包括堆叠在半导体衬底上的第一覆层，第一引导层，有源层，第二引导层和第二覆层。 第一包覆层，第一引导层，第二覆盖层和第二引导层的至少一部分具有超晶格结构。 另一半导体发光器件包括堆叠在半导体衬底上的缺陷分解层，缺陷阻挡层，第一覆层，有源层，第二覆层。 缺陷分解层和缺陷阻挡层包括超晶格结构。

公开(公告)号：US5418374A

公开(公告)日：1995-05-23

申请号：US70204

申请日：1993-06-02

申请人： Etsuo Morita ,  Shigetaka Tomiya ,  Tadashi Yamamoto ,  Akira Ishibashi

发明人： Etsuo Morita ,  Shigetaka Tomiya ,  Tadashi Yamamoto ,  Akira Ishibashi

IPC分类号： H01L21/205 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/80 ,  H01S5/00 ,  H01S5/22 ,  H01S5/223 ,  H01S5/32 ,  H01S5/323 ,  H01L33/00 ,  H01S3/19

CPC分类号： H01S5/32325 ,  H01S5/2232 ,  H01L33/16 ,  H01S5/2201 ,  H01S5/223 ,  H01S5/2235 ,  H01S5/3202

摘要： A ridge or groove is formed on a major surface of a semiconductor substrate which is formed on a first electrode and whose major surface having a ridge or groove is slanted to a crystal axis direction from a {001} crystal plane. A first semiconductor layer is formed on the semiconductor substrate, then a semiconductor function layer deviating from a {111} B crystal plane is formed on the first semiconductor layer, then a second semiconductor layer is formed on the semiconductor function layer and then a second electrode is formed on the second semiconductor layer. The ridge or groove extends to the crystal axis direction, and at least one of the first semiconductor layer, the semiconductor function layer and the second semiconductor layer includes phosphorus.

摘要翻译： 在第一电极上形成的半导体衬底的主表面上的脊或沟槽，其主表面具有脊或沟槽，从{001}晶面倾斜到晶体轴方向。 在半导体衬底上形成第一半导体层，然后在第一半导体层上形成偏离{111} B晶面的半导体功能层，然后在半导体功能层上形成第二半导体层，然后形成第二电极 形成在第二半导体层上。 脊或槽延伸到<110>晶轴方向，并且第一半导体层，半导体功能层和第二半导体层中的至少一个包括磷。

公开(公告)号：US08741451B2

公开(公告)日：2014-06-03

申请号：US11976246

申请日：2007-10-23

申请人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

发明人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

IPC分类号： B32B9/00 ,  B32B19/00

CPC分类号： H01L21/02538 ,  C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265

摘要： A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces (13a), (13b) in an end of each threading dislocation D1 elongating from below. The threading dislocation D1 is separated from the upper layer by the spaces (13a), (13b), so that each threading dislocation D1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D1 expressed by Burgers vector is preserved to develop another dislocation, the spaces (13a), (13b) vary the direction of its displacement. As a result, the upper layer above the spaces (13a), (13b) turns crystalline with a low dislocation density.

摘要翻译： 使用具有位错的晶体基底来获得位错密度低的晶体膜，晶体基板和半导体器件。 生长衬底（11）的一侧设置有在其间具有缓冲层（12）的晶体层（13）。 在从下方延伸的每个穿透位错D1的端部中，晶体层（13）具有空间（13a），（13b）。 穿透位错D1通过空间（13a），（13b）与上层分开，使得每个穿透位错D1被阻止传播到上层。 当由汉堡矢量表示的穿透位错D1的位移被保留以产生另一个位错时，空间（13a），（13b）改变其位移的方向。 结果，空间（13a），（13b）上方的上层以低位错密度变成结晶。

公开(公告)号：US07294201B2

公开(公告)日：2007-11-13

申请号：US09728193

申请日：2000-11-30

申请人： Etsuo Morita

发明人： Etsuo Morita

IPC分类号： C30B25/04

CPC分类号： H01L21/0237 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  Y10T428/24273 ,  Y10T428/24802

摘要： A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations as well as a method of manufacturing a crystal and a method of manufacturing a device with the use thereof are disclosed. On a basal body, formed in order are a base crystal layer of, for example, gallium nitride (GaN), a first mask pattern of, for example, silicon dioxide (SiO2), an intermediate crystal layer of, for example, gallium nitride, a second mask pattern of, for example, silicon dioxide, and a top crystal layer of, for example, gallium nitride. The first and second mask patterns have stripes arranged at least in one direction at unequally spaced intervals. The stripes are different in pitch from pattern to pattern. Thus, the mask patterns at least partly overlie one another in the direction of the thickness of the crystal layers.

摘要翻译： 公开了一种晶体衬底和易于制造并且具有很少位错的氮化物系III-V族化合物的结晶膜以及晶体的制造方法及使用该器件的制造方法。 在基体上依次形成例如氮化镓（GaN）的基底层，例如二氧化硅（SiO 2）的第一掩模图案，中间晶体 例如氮化镓，例如二氧化硅的第二掩模图案，以及例如氮化镓的顶部晶体层。 第一和第二掩模图案具有至少沿一个方向以不等间隔布置的条纹。 条纹与图案之间的间距不同。 因此，掩模图案在晶体层的厚度方向上至少部分地彼此叠置。

公开(公告)号：US20070125996A1

公开(公告)日：2007-06-07

申请号：US11699999

申请日：2007-01-31

申请人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

发明人： Etsuo Morita ,  Yousuke Murakami ,  Goshi Biwa ,  Hiroyuki Okuyama ,  Masato Doi ,  Toyoharu Oohata

IPC分类号： H01L29/06 ,  H01L33/00 ,  H01L31/00 ,  H01L29/739

CPC分类号： H01L21/02538 ,  C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265

摘要： A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces (13a), (13b) in an end of each threading dislocation D1 elongating from below. The threading dislocation D1 is separated from the upper layer by the spaces (13a), (13b), so that each threading dislocation D1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D1 expressed by Burgers vector is preserved to develop another dislocation, the spaces (13a), (13b) vary the direction of its displacement. As a result, the upper layer above the spaces (13a), (13b) turns crystalline with a low dislocation density.

摘要翻译： 使用具有位错的晶体基底来获得位错密度低的晶体膜，晶体基板和半导体器件。 生长衬底（11）的一侧设置有在其间具有缓冲层（12）的晶体层（13）。 晶体层（13）在从下方延伸的每个穿透位错D 1 1的末端具有间隔（13a），（13b）。 穿透位错D 1＆lt; 1＆gt;通过空间（13a），（13b）从上层分离，使得每个穿透位错D 1 1被阻止传播到 上层。 当由汉堡矢量表示的穿透位错D 1 1的位移被保留以产生另一位错时，空间（13a），（13b）改变其位移的方向。 结果，空间（13a），（13b）上方的上层以低位错密度变为结晶。