专利检索 ap:("Hisham Abu Salah" OR "Eliezer Weissmann" OR "Efraim Rotem" OR "Paul S. Diefenbaugh" OR "Jay D. Schwartz" OR "Sharad C. Tripathi") AND inv:"Efraim Rotem" 第 1 页

1.

发明授权
Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power 有权

公开(公告)号：US09600058B2

公开(公告)日：2017-03-21

申请号：US14313597

申请日：2014-06-24

申请人： Hisham Abu Salah , Eliezer Weissmann , Efraim Rotem , Paul S. Diefenbaugh , Jay D. Schwartz , Sharad C. Tripathi

发明人： Hisham Abu Salah , Eliezer Weissmann , Efraim Rotem , Paul S. Diefenbaugh , Jay D. Schwartz , Sharad C. Tripathi

IPC分类号： G06F1/32

CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3293 , Y02D10/126

摘要： Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

2.

发明申请
Forcing A Processor Into A Low Power State 有权
标题翻译：将处理器强制为低功耗状态

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon

发明人： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。描述和要求保护其他实施例。

3.

发明授权
Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation 有权
标题翻译：节能，节能，包括螺纹固结的方法，装置和系统

公开(公告)号：US09075610B2

公开(公告)日：2015-07-07

申请号：US13327692

申请日：2011-12-15

申请人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman

发明人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman

IPC分类号： G06F1/26 , G06F1/32

CPC分类号： G06F1/3243 , G06F1/3234 , Y02D10/152 , Y02D50/20

摘要： An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.

摘要翻译： 这里描述了用于线程合并的装置，方法和系统。当前的处理器利用率得到确定。并且从处理器利用率和其他执行参数来识别合并机会，例如在合并之后估计新的利用率，确定基于新利用率是否能够节省能源，以及执行线程迁移/合并到活动处理元件的子集。一旦执行整合，现在处于空闲状态的非子集处理元件被关闭以节省能量并提供节能的执行环境。

4.

发明申请
Controlling Forced Idle State Operation In A Processor 审中-公开

公开(公告)号：US20170371399A1

公开(公告)日：2017-12-28

申请号：US15190377

申请日：2016-06-23

申请人： Eliezer Weissmann , Efraim Rotem , Yoni Aizik , Doron Rajwan , Gal Leibovich , Nadav Shulman , Hisham Abu Salah

发明人： Eliezer Weissmann , Efraim Rotem , Yoni Aizik , Doron Rajwan , Gal Leibovich , Nadav Shulman , Hisham Abu Salah

IPC分类号： G06F1/32 , G06F13/24 , G06F1/26

CPC分类号： G06F1/3287 , G06F1/266 , G06F13/24 , Y02D10/14

摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

5.

发明授权
Providing an asymmetric multicore processor system transparently to an operating system 有权

公开(公告)号：US09720730B2

公开(公告)日：2017-08-01

申请号：US13995994

申请日：2011-12-30

申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest

发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest

IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F9/30 , G06F15/78

CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32

摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

6.

发明申请
PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM 有权
标题翻译：向操作系统提供不对称的多重处理器系统

公开(公告)号：US20140082630A1

公开(公告)日：2014-03-20

申请号：US13995994

申请日：2011-12-30

申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest

发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest

IPC分类号： G06F9/48

CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32

摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。第二组可以是与第一组或同一ISA组不同的指令集架构（ISA），但具有不同的功率和性能支持级别，并且对于操作系统（OS）是透明的。处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。这种基于动态硬件的上下文切换对于操作系统可以是透明的。描述和要求保护其他实施例。

7.

发明申请
METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING THREAD CONSOLIDATION 有权
标题翻译：能源效率和能源保护的方法，装置和系统，包括螺纹综合

公开(公告)号：US20120185709A1

公开(公告)日：2012-07-19

申请号：US13327692

申请日：2011-12-15

申请人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman

发明人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman

IPC分类号： G06F1/32

CPC分类号： G06F1/3243 , G06F1/3234 , Y02D10/152 , Y02D50/20

摘要： An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.

摘要翻译： 这里描述了用于线程合并的装置，方法和系统。当前的处理器利用率得到确定。并且从处理器利用率和其他执行参数来识别合并机会，例如在合并之后估计新的利用率，确定基于新利用率是否能够节省能源，以及执行线程迁移/合并到活动处理元件的子集。一旦执行整合，现在处于空闲状态的非子集处理元件被关闭以节省能量并提供节能的执行环境。

8.

发明授权
Dynamically controlling cache size to maximize energy efficiency 有权
标题翻译：动态控制缓存大小以最大限度提高能效

公开(公告)号：US09158693B2

公开(公告)日：2015-10-13

申请号：US13285465

申请日：2011-10-31

申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah

发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah

IPC分类号： G06F12/00 , G06F12/08

CPC分类号： G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13

摘要： In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。描述和要求保护其他实施例。

9.

发明申请
CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS 审中-公开
标题翻译：通过多个时间间隔的多个功率限制来控制功耗

公开(公告)号：US20130173946A1

公开(公告)日：2013-07-04

申请号：US13340433

申请日：2011-12-29

申请人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Eliezer Weissmann , Alon Naveh , James G. Hermerding, II , Riad Durr , Hisham Abu Salah

发明人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Eliezer Weissmann , Alon Naveh , James G. Hermerding, II , Riad Durr , Hisham Abu Salah

IPC分类号： G06F1/26

CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171

摘要： Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了通过多个时间间隔通过多个功率限制来控制功耗的方法和装置。在一个实施例中，基于所确定的功率限制值来修改计算设备组件（例如，处理器或其处理器核心之一）的功率消耗水平。功率极限值可以基于多个时间间隔上的滚动功率消耗平均值和它们与多个对应功率限制的比较来确定。还公开并要求保护其他实施例。