公开(公告)号：US09991190B2

公开(公告)日：2018-06-05

申请号：US13475674

申请日：2012-05-18

Applicant: Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

Inventor： Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/495 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

公开(公告)号：US08519526B2

公开(公告)日：2013-08-27

申请号：US13112226

申请日：2011-05-20

Applicant: Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L23/48

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。

公开(公告)号：US20120129315A1

公开(公告)日：2012-05-24

申请号：US12930659

申请日：2011-01-12

Applicant: Yeh-Chang Hu ,  Chung-Tang Lin ,  Hui-Min Huang ,  Yih-Jenn Jiang ,  Shih-Kuang Chiu

Inventor： Yeh-Chang Hu ,  Chung-Tang Lin ,  Hui-Min Huang ,  Yih-Jenn Jiang ,  Shih-Kuang Chiu

IPC: H01L21/50

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board.

Abstract translation: 一种制造半导体封装的方法，包括以下步骤：提供具有分别对应于开口的多个开口和多个对准标记的对准板; 在对准基板上根据对准标记在与开口相对应的位置处设置多个芯片; 用具有设置在其一个表面上的软层的载板压住对准板，以将芯片嵌入载板的软层中; 并拆下对准板。 因此，芯片的位置根据对准板上的对准标记精确地定位。

公开(公告)号：US09576830B2

公开(公告)日：2017-02-21

申请号：US13475790

申请日：2012-05-18

Applicant: Hui-Min Huang ,  Chih-Wei Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Hui-Min Huang ,  Chih-Wei Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/67288 ,  H01L21/6838

Abstract: A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.

Abstract translation: 一种用于调整晶片翘曲的方法，包括提供具有中心部分和边缘部分的晶片，并提供其上具有用于保持晶片的保持区域的保持台。 将晶片放置在保持台上，其中心部分高​​于边缘部分，然后按压到保持区域上，使得晶片通过自吸力被吸引并保持在保持台上。 根据晶片的翘曲量将晶片在预定温度下加热预定时间，以便实现基本上平坦的晶片或预定的晶片级。

公开(公告)号：US20140008786A1

公开(公告)日：2014-01-09

申请号：US13544783

申请日：2012-07-09

Applicant: Meng-Tse Chen ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Hui-Min Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Hui-Min Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/3157 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

Abstract translation: 一种装置包括第一包装部件和第一包装部件的顶表面上的第一金属痕迹和第二金属迹线。 该装置还包括覆盖第一封装部件的顶表面，第一金属迹线和第二金属迹线的介电掩模层，其中介电掩模层具有其中的开口露出第一金属迹线。 该器件还包括形成在第二封装元件上的第二封装元件和互连，所述互连件具有形成在所述金属突起上的金属突起和焊料凸块，其中所述焊料凸点接触所述介电掩模的开口中的所述第一金属迹线 层。

公开(公告)号：US20100052360A1

公开(公告)日：2010-03-04

申请号：US12199136

申请日：2008-08-27

Applicant: Chih-Cheng Hsu ,  Albert H. Butlin ,  John E. Carsley ,  Hui-Min Huang ,  Stephen R. Koshorek ,  John N. Owens

Inventor： Chih-Cheng Hsu ,  Albert H. Butlin ,  John E. Carsley ,  Hui-Min Huang ,  Stephen R. Koshorek ,  John N. Owens

IPC: B62D25/04

CPC classification number: B60R21/0428 ,  B60J5/0437 ,  B60J5/044 ,  B60J5/0455 ,  B60R2021/0006

Abstract: A door assembly for a vehicle includes an outer panel. A support panel is operatively connected to the outer panel and configured such that the support panel provides bending resistance to the outer panel when the outer panel is deflected toward the support panel during a first deflection distance of the outer panel. A cable is operatively connected in the door assembly between a first end and a second end of the outer panel such that the cable provides additional bending resistance to the outer panel when the outer panel is deflected toward the support panel during a second deflection distance of the outer panel, greater than the first deflection distance.

Abstract translation: 用于车辆的门组件包括外板。 支撑面板可操作地连接到外部面板并且构造成使得当外部面板在外部面板的第一偏转距离期间偏转到支撑面板时，支撑面板向外部面板提供抗弯曲性。 电缆在门组件中可操作地连接在外板的第一端和第二端之间，使得当外板在外板的第二偏转距离期间朝向支撑板偏转时，电缆向外板提供额外的弯曲阻力 外面板，大于第一偏转距离。

公开(公告)号：US10192804B2

公开(公告)日：2019-01-29

申请号：US13544783

申请日：2012-07-09

Applicant: Meng-Tse Chen ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Hui-Min Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Hui-Min Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L29/49 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

公开(公告)号：US08603911B2

公开(公告)日：2013-12-10

申请号：US13105338

申请日：2011-05-11

Applicant: Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

Inventor： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

IPC: H01L21/44 ,  H01L23/12 ,  H01L29/40

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract translation: 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

公开(公告)号：US08564343B2

公开(公告)日：2013-10-22

申请号：US13422772

申请日：2012-03-16

Applicant: Hui-Min Huang

Inventor： Hui-Min Huang

IPC: H03L7/06

CPC classification number: H03L7/10 ,  H03L7/0891

Abstract: Nowadays, electronic product designs are aimed at saving, due to the trend to reduce energy consumption and carbon output. Ethernet technology has also been aimed specifically at saving energy; IEEE P802.3az standard (Energy Efficient Ethernet, EEE), for Ethernet released by Broadcom is one example. The disclosure turns off the phase-locked loop when the network communication stops, effectively saving the energy consumption of the network chip under the EEE standard. In the case of network reconnection, the disclosure turns on the phase-locked loop to start the network communication through adjusting the current of current source and the parameters of a low pass filter to increase the charging speed for the reference voltage generation of the low pass filter. The disclosure then shortens the start-up time to quickly output the standard output frequency and phase of the phase-locked loop.

Abstract translation: 目前，电子产品设计的目的是为了节约能源，因为降低能耗和碳输出的趋势。 以太网技术也专门用于节约能源; Broadcom发布的以太网发布的IEEE P802.3az标准（Energy Efficient Ethernet，EEE）就是一个例子。 当网络通信停止时，本公开将关闭锁相环，有效地节省了EEE标准下网络芯片的能耗。 在网络重新连接的情况下，本公开通过调节电流源的电流和低通滤波器的参数来开启锁相环以开始网络通信，以增加用于低通的参考电压产生的充电速度 过滤。 该公开然后缩短启动时间以快速输出锁相环的标准输出频率和相位。

公开(公告)号：US09349663B2

公开(公告)日：2016-05-24

申请号：US13539136

申请日：2012-06-29

Applicant: Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set of conductive elements coupling the first package component to the second package component. A first polymer-comprising material is molded on the first package component and surrounds the first set of conductive elements. The first polymer-comprising material has an opening therein exposing a top surface of the second package component. A third package component and a second set of conductive elements couples the second package component to the third package component.

Abstract translation: 提供机械强度和翘曲控制的封装结构的封装包括第一封装元件，第二封装元件和将第一封装元件连接到第二封装元件的第一组导电元件。 第一含聚合物的材料被模制在第一包装部件上并包围第一组导电元件。 第一含聚合物的材料在其中具有露出第二包装部件的顶表面的开口。 第三包装部件和第二组导电元件将第二包装部件耦合到第三包装部件。