公开(公告)号：US20170018517A1

公开(公告)日：2017-01-19

申请号：US15203013

申请日：2016-07-06

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Liang WANG ,  Arkalgud R. SITARAM

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Abstract translation: 两个微电子部件（110,120），例如 模具和插入件彼此结合。 部件的接触焊盘（110C）中的一个包括金属，另一部件具有与金属反应形成金属硅化物（504）的硅（410）。 然后通过其中一个部件制成一个孔（510），以到达金属硅化物，甚至可能连接另一部件的未反应的金属（110C）。 该孔填充有可能是金属的导体（130），以提供可电耦合到可附接到其它电路元件或微电子部件的接触焊盘（120C.B）的导电通孔，例如。 到印刷电路板。

公开(公告)号：US20190157199A1

公开(公告)日：2019-05-23

申请号：US16238786

申请日：2019-01-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM ,  Hong Shen ,  Zhuowen SUN ,  Liang WANG ,  Guilian GAO

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20170084539A1

公开(公告)日：2017-03-23

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian GAO ,  Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Hong SHEN ,  Arkalgud R. SITARAM ,  Liang WANG ,  Akash AGRAWAL ,  Rajesh KATKAR

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

公开(公告)号：US20180130717A1

公开(公告)日：2018-05-10

申请号：US15865842

申请日：2018-01-09

Applicant: INVENSAS CORPORATION

Inventor： Hong SHEN ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM

IPC: H01L23/055 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L21/288 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

公开(公告)号：US20160163650A1

公开(公告)日：2016-06-09

申请号：US14704714

申请日：2015-05-05

Applicant: Invensas Corporation

Inventor： Guilian GAO ,  Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Hong SHEN ,  Arkalgud R. SITARAM ,  Liang WANG ,  Akash AGRAWAL ,  Rajesh KATKAR

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract translation: 模具（110）和/或未开封的晶片和/或多芯片模块（MCM）被附接在插入器（120）或一些其它结构（例如另一集成电路）的顶部上并被密封剂（160）覆盖。 然后插入器从下面变薄。 在封装之前，在封装周围的插入件周围形成比密封剂更刚性的层（410），以通过机械工艺（例如CMP）来减小或消除插入件在裸片间的凹陷。 还提供其他功能。

公开(公告)号：US20160013151A1

公开(公告)日：2016-01-14

申请号：US14328380

申请日：2014-07-10

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract translation: 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。

公开(公告)号：US20180233447A1

公开(公告)日：2018-08-16

申请号：US15952935

申请日：2018-04-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM ,  Hong SHEN ,  Zhuowen SUN ,  Liang WANG ,  Guilian GAO

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20170278787A1

公开(公告)日：2017-09-28

申请号：US15619160

申请日：2017-06-09

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM ,  Hong SHEN ,  Zhuowen SUN ,  Liang WANG ,  Guilian GAO

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20160379885A1

公开(公告)日：2016-12-29

申请号：US14749529

申请日：2015-06-24

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Guilian GAO ,  Liang WANG ,  Hong SHEN ,  Arkalgud R. SITARAM

IPC: H01L21/82 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522

CPC classification number: H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Abstract translation: 一种形成该器件的器件和方法，该器件包括形成在衬底器件的衬底中的腔体，该衬底器件还包括形成在衬底中的导电通孔。 芯片器件，晶片和其他衬底器件可以安装到衬底器件上。 可以在衬底装置上形成封装层和材料以便填充空腔。