公开(公告)号：US06962876B2

公开(公告)日：2005-11-08

申请号：US10981731

申请日：2004-11-05

申请人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

IPC分类号： C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318 ,  H01L21/321 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0228 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02274 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211

摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

公开(公告)号：US20050148201A1

公开(公告)日：2005-07-07

申请号：US10981731

申请日：2004-11-05

申请人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

IPC分类号： C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318 ,  H01L21/321 ,  H01L21/44

CPC分类号： H01L21/0228 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02274 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211

摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

摘要翻译： 一种用于使用ALD工艺形成用于半导体器件的低k电介质层的方法，包括（a）在半导体衬底上形成预定的互连图案，（b）向其中具有衬底的室提供第一和第二反应性材料， 从而将第一和第二反应性材料吸附在衬底的表面上，（c）向腔室供应第一气体以清除保留未反应的第一和第二反应性材料，（d）向室提供第三反应性材料，从而 引起所述第一和第二材料和所述第三反应性材料之间的反应以形成单层，（e）向所述室供应第二气体以吹扫在所述室中保留未反应的第三反应性材料和副产物; 和（f）重复（b）至（e）预定次数以在基板上形成具有预定厚度的SiBN三元层。

公开(公告)号：US06740977B2

公开(公告)日：2004-05-25

申请号：US10422283

申请日：2003-04-24

申请人： Jae-Young Ahn ,  Yong-Woo Hyung ,  Young-Seok Kim ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Yong-Woo Hyung ,  Young-Seok Kim ,  Man-Sug Kang

IPC分类号： H01L2348

CPC分类号： H01L21/022 ,  C23C16/342 ,  C23C16/345 ,  C23C16/45529 ,  C23C16/45536 ,  H01L21/02112 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/3192 ,  H01L23/53295 ,  H01L29/511 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： The present invention discloses a novel insulating layer for use in semiconductor devices, the insulating layer having a multi-layer nanolaminate structure consisting of alternating boron nitride thin films and silicon nitride thin films, each of a controlled, desired thickness, together with methods for forming the same. The insulating layer of the present invention has a multi-layer nanolaminate structure consisting of alternating boron nitride thin films and silicon nitride thin filmsformed by the steps of: (a) depositing a silicon nitride thin film on a wafer, (b) depositing a boron nitride thin film on the silicon nitride thin film, and (c) forming the multi-layer nanolaminate thin film by alternately repeating steps (a) and (b).

摘要翻译： 本发明公开了一种用于半导体器件的新型绝缘层，该绝缘层具有由交替的氮化硼薄膜和氮化硅薄膜组成的多层纳米层状结构，每个都具有可控制的期望厚度，以及形成方法 本发明的绝缘层具有由交替的氮化硼薄膜和氮化硅薄膜组成的多层纳米层状结构，其形成步骤如下：（a）在晶片上沉积氮化硅薄膜，（b） 在氮化硅薄膜上沉积氮化硼薄膜，（c）通过交替重复步骤（a）和（b）形成多层纳米级氨基酸盐薄膜。

公开(公告)号：US06815350B2

公开(公告)日：2004-11-09

申请号：US10378681

申请日：2003-03-05

申请人： Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sung Kang ,  Jae-Young Ahn

发明人： Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sung Kang ,  Jae-Young Ahn

IPC分类号： H01L2131

CPC分类号： H01L21/0228 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02112 ,  H01L21/02274 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211

摘要： A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.

公开(公告)号：US08241979B2

公开(公告)日：2012-08-14

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/8234

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US07723182B2

公开(公告)日：2010-05-25

申请号：US11291798

申请日：2005-11-30

申请人： Won-Jun Jang ,  In-Sun Park ,  Jae-Young Park ,  Ki-Vin Im ,  Yong-Woo Hyung

发明人： Won-Jun Jang ,  In-Sun Park ,  Jae-Young Park ,  Ki-Vin Im ,  Yong-Woo Hyung

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.

摘要翻译： 在一个实施例中，半导体器件中的电容器的存储电极在其制造工艺期间耐受无意的蚀刻。 描述形成电容器的存储电极的方法。 电容器的存储电极可以包括通过穿过半导体衬底上的绝缘层的接触插塞与晶体管的源极区域电连接的第一金属层。 然后可以在第一金属层上形成多晶硅层。 在多晶硅层上形成第二金属层。

公开(公告)号：US20090108323A1

公开(公告)日：2009-04-30

申请号：US12228772

申请日：2008-08-15

申请人： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

发明人： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC分类号： H01L29/788 ,  H01L21/3215 ,  H01L21/22

CPC分类号： H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

摘要： A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

摘要翻译： 提供一种制造非易失性存储器件的方法。 该方法包括形成在衬底上限定有源区的隔离图案，在有源区上形成浮置栅极图案，以及在浮栅图案上形成栅极线。 浮置栅极图案在有源区域上是自对准的，并且当浮栅图案更靠近有源区域时，其杂质离子浓度变得相对较低。

公开(公告)号：US20070059889A1

公开(公告)日：2007-03-15

申请号：US11531239

申请日：2006-09-12

申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to the presence of impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于在第二多晶硅层中存在杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20060003509A1

公开(公告)日：2006-01-05

申请号：US11175569

申请日：2005-07-05

申请人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Yong-Woo Hyung ,  Jai-Dong Lee ,  Ki-Su Na ,  Jung-Hwan Kim

发明人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Yong-Woo Hyung ,  Jai-Dong Lee ,  Ki-Su Na ,  Jung-Hwan Kim

IPC分类号： H01L21/76 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28247 ,  H01L27/11568 ,  H01L29/4933

摘要： In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

摘要翻译： 在一个实施例中，形成用于半导体器件的栅极结构的方法包括在半导体衬底上形成初步栅极结构。 预栅极结构包括依次层叠在基板上的栅极氧化物图案和导电图案。 然后，使用包含至少一个氧原子的氧自由基对具有预选择门结构的基板进行再氧化处理，从而在基板的表面和预选择门结构的侧壁上形成氧化物层，形成 半导体器件的栅极结构。 防止栅极氧化物图案的厚度增加，并且提高氧化物层的质量。

公开(公告)号：US20100323489A1

公开(公告)日：2010-12-23

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.