公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09025340B2

公开(公告)日：2015-05-05

申请号：US14042628

申请日：2013-09-30

申请人： Jason R. Wright ,  Michael B. Vincent ,  Weng F. Yap

发明人： Jason R. Wright ,  Michael B. Vincent ,  Weng F. Yap

IPC分类号： H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H05K1/09 ,  H05K3/12 ,  H05K3/14 ,  H05K3/26 ,  H05K3/04 ,  H05K3/06 ,  H05K3/08

CPC分类号： H05K3/403 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/045 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/4916 ,  H01L2924/00

摘要： Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

摘要翻译： 用于形成微电子器件封装的方法的实施例包括在第一和第二器件对边缘导体的暴露端之间的封装主体的表面上形成沟槽，以及在沟槽中形成封装表面导体以电耦合第一和第二器件 到边缘导体。 在一个实施例中，封装表面导体通过首先在封装表面上形成导电材料层而形成，其中导电材料层基本上填充沟槽，并且随后将导电材料层的部分从与沟槽相邻的封装表面移除。 在另一个实施例中，通过在第一和第二暴露端之间的沟槽中分配一个或多个导电材料来形成封装表面导体（例如，使用诸如喷涂，喷墨印刷，气溶胶喷射印刷，模板印刷或针分配的技术 ）。 然后可以从邻近沟槽的封装表面移除过量的导电材料。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US20150092377A1

公开(公告)日：2015-04-02

申请号：US14042628

申请日：2013-09-30

申请人： JASON R. WRIGHT ,  Michael B. Vincent ,  Weng F. Yap

发明人： JASON R. WRIGHT ,  Michael B. Vincent ,  Weng F. Yap

IPC分类号： H05K1/11 ,  H05K3/12 ,  H05K3/08 ,  H05K3/26 ,  H05K3/04 ,  H05K3/06 ,  H05K1/09 ,  H05K3/14

CPC分类号： H05K3/403 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/045 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/4916 ,  H01L2924/00

摘要： Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

摘要翻译： 用于形成微电子器件封装的方法的实施例包括在第一和第二器件对边缘导体的暴露端之间的封装主体的表面上形成沟槽，以及在沟槽中形成封装表面导体以电耦合第一和第二器件 到边缘导体。 在一个实施例中，封装表面导体通过首先在封装表面上形成导电材料层而形成，其中导电材料层基本上填充沟槽，并且随后将导电材料层的部分从与沟槽相邻的封装表面移除。 在另一个实施例中，通过在第一和第二暴露端之间的沟槽中分配一个或多个导电材料来形成封装表面导体（例如，使用诸如喷涂，喷墨印刷，气溶胶喷射印刷，模板印刷或针分配的技术 ）。 然后可以从邻近沟槽的封装表面移除过量的导电材料。

公开(公告)号：US09305911B2

公开(公告)日：2016-04-05

申请号：US14097459

申请日：2013-12-05

申请人： Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/538 ,  H01L23/02 ,  H01L23/48 ,  H01L21/00 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L25/50 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

摘要： Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

摘要翻译： 用于形成微电子器件封装的方法的实施例包括在第一和第二封装表面导体将（或已经）形成在沟槽的两侧上的邻近区域中在封装主体的表面上形成沟槽。 该方法还包括形成第一和第二封装表面导体以电耦合器件对边缘导体的各种组合的暴露端。 沟槽可以使用激光切割，钻孔，锯切，蚀刻或其它合适的技术形成。 封装表面导体可以通过在器件 - 表面导体的暴露端之间的封装主体表面上分配（例如，涂覆，喷涂，喷墨印刷，喷雾印刷，模版印刷或针分配）形成一个或多个导电材料， 边缘导体。

公开(公告)号：US09299670B2

公开(公告)日：2016-03-29

申请号：US13829737

申请日：2013-03-14

申请人： Weng F. Yap ,  Michael B. Vincent ,  Jason R. Wright

发明人： Weng F. Yap ,  Michael B. Vincent ,  Jason R. Wright

IPC分类号： H01L23/28 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/565 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/06182 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82365 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/0665

摘要： A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.

摘要翻译： 堆叠的微电子封装可以包括具有外部垂直封装侧壁的封装主体，嵌入封装体内的多个微电子器件，以及电耦合到多个微电子器件并延伸到外部垂直封装侧壁的封装边缘导体。 在包装体的第一个封装边缘导体和第二封装边缘导体之间的封装主体的外表面上形成一个空腔。 导电材料在空腔中并与第一和第二封装边缘导体电接触，其中空腔中的导电材料在微电子封装的平面形状尺寸内。

公开(公告)号：US09524950B2

公开(公告)日：2016-12-20

申请号：US13906621

申请日：2013-05-31

申请人： Weng F. Yap ,  Michael B. Vincent

发明人： Weng F. Yap ,  Michael B. Vincent

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC分类号： H01L24/97 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1815 ,  H01L2924/00

摘要： A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.

摘要翻译： 一种用于制造堆叠的微电子器件的方法包括将第一封装层附接到第二封装层以形成堆叠的微电子层。 第一包装层的锯街道覆盖并与第二包装层的锯切街道对齐。 第一和第二封装层包括形成在第一和第二封装层中的锯条和电子部件之间的相应的边缘连接器。 通过包装通孔形成在第一和第二包装层的锯条之一中。 通孔填充有导电材料。 堆叠的封装层沿着锯条街道以保持导电材料的一部分以在至少两个边缘连接器之间形成侧壁连接器的方式被切割。

公开(公告)号：US09362234B2

公开(公告)日：2016-06-07

申请号：US14149335

申请日：2014-01-07

申请人： Eduard J. Pabst ,  Sergio P. Pacheco ,  Weng F. Yap

发明人： Eduard J. Pabst ,  Sergio P. Pacheco ,  Weng F. Yap

IPC分类号： H01L23/552 ,  H01L21/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/12105

摘要： Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.

摘要翻译： 提供了屏蔽器件封装和相关的制造方法。 示例性的器件封装包括一个或多个电气部件，覆盖所述一个或多个电气部件的模制化合物，所述模制化合物内的导电互连结构，横向围绕所述一个或多个电部件和所述互连结构的导电框架结构，以及 覆盖一个或多个电气部件的屏蔽结构。 屏蔽结构电连接到框架结构，并且模制化合物的至少一部分位于屏蔽结构和一个或多个电气部件之间。

公开(公告)号：US09281286B1

公开(公告)日：2016-03-08

申请号：US14470679

申请日：2014-08-27

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/03466 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014

摘要： Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

摘要翻译： 提供了微电子封装和用于制造具有纹理化焊盘的微电子封装的方法，其可以提高焊点可靠性。 在一个实施例中，该方法包括在下焊盘电介质层中形成具有纹理图案（例如阴影图案）的纹理化电介质区域。 在纹理化电介质区域上产生纹理化的焊盘。 纹理化焊料焊盘具有焊接接触表面，纹理图案被转印到该焊接接触表面，使得焊料接触表面的面积相对于等效尺寸的非变形焊料垫而增加。