公开(公告)号：US06373717B1

公开(公告)日：2002-04-16

申请号：US09540172

申请日：2000-03-31

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K118

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

公开(公告)号：US07024764B2

公开(公告)日：2006-04-11

申请号：US10040745

申请日：2002-01-07

申请人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K3/34

CPC分类号： H01L23/49822 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

摘要翻译： 制作电子包装的方法。 该方法包括形成半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 形成的多层互连结构适于将半导体芯片与另外多个焊接连接的电路化基板（例如，电路板）电互连，并且包括导热层，其由具有选定厚度和系数的材料组成 热膨胀以基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 该方法形成电子封装以进一步包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。

公开(公告)号：US06829823B2

公开(公告)日：2004-12-14

申请号：US10067551

申请日：2002-02-05

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01K310

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

摘要翻译： 一种制造多层互连结构的方法。 第一和第二导电构件分别形成在第一和第二电介质层上。 电介质层形成在导热层的相对表面上。 第一和第二导电层形成在第一介电层内。 第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。 通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。 形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

公开(公告)号：US06351393B1

公开(公告)日：2002-02-26

申请号：US09346356

申请日：1999-07-02

申请人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K114

CPC分类号： H01L23/49822 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

摘要翻译： 提供电子封装和制造电子封装的方法。 封装包括半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 多层互连结构适于将半导体芯片与另外多个焊料连接的电路化基板（例如，电路板）电互连，并且包括由具有选定厚度和热系数的材料组成的导热层 从而基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 电子封装还包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。

公开(公告)号：US06562654B2

公开(公告)日：2003-05-13

申请号：US09829469

申请日：2001-04-09

申请人： John S. Kresge ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01L2144

CPC分类号： H01L23/49894 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H05K1/114 ,  H05K3/0094 ,  H05K2201/0154 ,  H05K2201/10734 ,  H05K2203/1394

摘要： A process for tenting through-holes comprises providing a circuitized substrate having a plurality of plated through-holes, wherein the plated through-holes are tented with a polyimide material.

摘要翻译： 一种用于穿透通孔的方法包括提供具有多个电镀通孔的电路化基板，其中所述电镀通孔与聚酰亚胺材料搭配。

公开(公告)号：US06249045B1

公开(公告)日：2001-06-19

申请号：US09416284

申请日：1999-10-12

申请人： John S. Kresge ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01L2144

CPC分类号： H01L23/49894 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H05K1/114 ,  H05K3/0094 ,  H05K2201/0154 ,  H05K2201/10734 ,  H05K2203/1394

摘要： A circuitized substrate having plated through-holes wherein the plated through-holes are, tented with a polyimide material is provided along with the process for fabricating such.

摘要翻译： 具有电镀通孔的电路化基板与其制造方法一起提供，其中电镀通孔与聚酰亚胺材料一起配置。

公开(公告)号：US06228470B1

公开(公告)日：2001-05-08

申请号：US09110914

申请日：1998-07-06

申请人： John S. Kresge ,  James R. Wilcox

发明人： John S. Kresge ,  James R. Wilcox

IPC分类号： B32B1504

CPC分类号： B32B27/322 ,  B32B5/26 ,  B32B27/281 ,  H01L23/145 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/429 ,  H05K3/4641 ,  H05K3/4676 ,  H05K2201/0352 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/3154 ,  Y10T428/31544 ,  Y10T428/31678 ,  Y10T428/31681 ,  Y10T428/31699 ,  Y10T428/31721 ,  H01L2924/00

摘要： A substrate having enhanced mechanical rigidity and including high stiffness reinforcing layers, a conductive layer and non-cloth dielectric layers wherein the non-cloth dielectric layers have a modulus of elasticity which is less than the modulus of elasticity of the reinforcing layers and of the conductive layer. The high stiffness reinforcing layers are disposed off the neutral axis and away from the center of the organic substrate to increase the flexural rigidity and flexural yield strength of the organic substrate.

摘要翻译： 具有增强的机械刚性并且包括高刚度增强层，导电层和非布电介质层的基底，其中非布电介质层的弹性模量小于加强层的弹性模量和导电性 层。 高刚度加强层被设置在中性轴线之外并远离有机基底的中心，以增加有机基底的弯曲刚度和弯曲屈服强度。

公开(公告)号：US5874776A

公开(公告)日：1999-02-23

申请号：US840481

申请日：1997-04-21

申请人： John S. Kresge ,  James R. Wilcox

发明人： John S. Kresge ,  James R. Wilcox

IPC分类号： H01L23/373 ,  H01L23/498 ,  H05K1/02 ,  H05K1/05 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49827 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/05 ,  H05K3/3436

摘要： A substrate for connecting one element having a first coefficient of thermal expansion to another element having a differing coefficient of thermal expansion that will alleviate interconnection problems due to thermal mismatch.

摘要翻译： 用于将具有第一热膨胀系数的一个元件连接到具有不同热膨胀系数的另一元件的衬底，其将减轻由于热失配引起的互连问题。

公开(公告)号：US08240027B2

公开(公告)日：2012-08-14

申请号：US12007820

申请日：2008-01-16

申请人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

发明人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

IPC分类号： H01C17/06 ,  H01C17/24 ,  H01C17/242

CPC分类号： H01C17/06 ,  H01C17/24 ,  H05K1/0268 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0361 ,  H05K2203/171 ,  Y10T29/49099 ,  Y10T29/49101

摘要： A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

摘要翻译： 一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量 确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时 同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。

公开(公告)号：US20110284273A1

公开(公告)日：2011-11-24

申请号：US12782187

申请日：2010-05-18

申请人： Robert M. Japp ,  Kostas Papathomas ,  John S. Kresge ,  Timothy Antesberger

发明人： Robert M. Japp ,  Kostas Papathomas ,  John S. Kresge ,  Timothy Antesberger

IPC分类号： H05K1/09 ,  H05K1/00 ,  H01R43/00 ,  H05K1/11

CPC分类号： H05K3/4641 ,  H05K3/4617 ,  H05K2201/068 ,  Y10T29/49117

摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

摘要翻译： 适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。 芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。 导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。 还提供了制造电源芯和电路化基板的方法。 使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题 。