公开(公告)号：US20080006949A1

公开(公告)日：2008-01-10

申请号：US11765367

申请日：2007-06-19

Applicant: Jong-Gi LEE ,  Tae-Joo HWANG

Inventor： Jong-Gi LEE ,  Tae-Joo HWANG

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/16 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/83191 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括半导体芯片和多个导电球，例如形成在半导体芯片的接合表面上的焊球。 虚拟板包括与焊球对准的开口并且结合到半导体芯片的接合表面。 在半导体芯片和虚拟基板之间插入粘合材料，以将该虚拟板粘接到半导体芯片。 将粘合材料施加在粘附到半导体芯片的接合表面的伪板的粘合表面上。 将该虚拟板粘接到半导体芯片的接合面，使得焊球与开口对准。 可以选择性地使用廉价的底部填充材料，并且可以大大降低粘合剂材料的回流和固化的处理时间。

公开(公告)号：US20130078763A1

公开(公告)日：2013-03-28

申请号：US13618041

申请日：2012-09-14

Applicant: Jong-Gi LEE ,  Kwang-Yong Lee ,  Min-Ho Lee

Inventor： Jong-Gi LEE ,  Kwang-Yong Lee ,  Min-Ho Lee

IPC: H01L21/50

CPC classification number: H01L24/82 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/24998 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Abstract translation: 制备具有形成在其上表面上的第一突起电极的第一半导体芯片。 具有第二投影电极的第二半导体芯片安装在第一半导体芯片上以暴露第一投影电极。 在第一投影电极和第二投影电极之间形成绝缘膜。 在绝缘膜中形成凹槽。 形成了用于填充凹槽内部并连接到第一突出电极和第二突起电极的互连。

公开(公告)号：US20090026596A1

公开(公告)日：2009-01-29

申请号：US12178532

申请日：2008-07-23

Applicant: Sang-Wook PARK ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Sung-Ki LEE ,  Ji-Seok HONG

Inventor： Sang-Wook PARK ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Sung-Ki LEE ,  Ji-Seok HONG

IPC: H01L23/495 ,  H05K7/18

CPC classification number: H01L23/49555 ,  H01L23/49548 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In certain embodiments, a lead frame includes a paddle, a plurality of inner leads, first outer leads, and a second outer lead. The plurality of inner leads can be arranged at a side face of the paddle. The first outer leads can extend from the inner leads along a first direction and can be arranged at a substantially central portion of the side face of the paddle. Furthermore, each of the first outer leads can have a first area. The second outer lead can be arranged at an edge portion of the side face of the paddle and can be supported by the paddle. The second outer lead can have a second area that is larger than the first area.

Abstract translation: 在某些实施例中，引线框架包括桨，多个内引线，第一外引线和第二外导线。 多个内引线可以布置在桨的侧面。 第一外引线可以沿着第一方向从内引线延伸，并且可以布置在桨的侧面的大致中心部分。 此外，每个第一外引线可以具有第一区域。 第二外引线可以布置在桨的侧面的边缘部分处，并且可以由桨支撑。 第二外部引线可以具有大于第一区域的第二区域。

公开(公告)号：US20080308913A1

公开(公告)日：2008-12-18

申请号：US12140190

申请日：2008-06-16

Applicant: Sang-Wook PARK ,  Min-Young SON ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Sung-Ki LEE ,  Ji-Seok HONG

Inventor： Sang-Wook PARK ,  Min-Young SON ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Sung-Ki LEE ,  Ji-Seok HONG

IPC: H01L23/495

CPC classification number: H01L23/49555 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10757 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove.

Abstract translation: 叠层半导体封装包括第一半导体封装，第二半导体封装和导电连接构件。 第一半导体封装包括第一半导体芯片，具有与第一半导体芯片电连接的第一外部引线的第一引线框架和形成在第一半导体芯片和第一引线框架上以暴露第一外部引线的第一模制构件 。 第二半导体封装包括第二半导体芯片，形成在第一模制构件上的第二引线框架，并且具有可与第二半导体芯片电连接的第二外部引线，以及形成在第二半导体芯片上的第二模制构件和第二半导体芯片 引线框架露出第二个外引线。 导电连接构件可以将第一外引线和第二外引线彼此电连接。 此外，导电连接构件可以具有防裂槽。

公开(公告)号：US20080290513A1

公开(公告)日：2008-11-27

申请号：US12125391

申请日：2008-05-22

Applicant: Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

Inventor： Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the circuit patterns, and external contact terminals arranged on the portions of circuit patterns exposed by the openings; a semiconductor chip formed on a second surface of the semiconductor chip mounting member and electrically connected to the semiconductor chip mounting member; a first sealing portion coating the second surface of the semiconductor chip mounting member and the semiconductor chip; and a second sealing portion arranged on the insulating layer and the external contact terminals such that at least portions of the external contact terminals are exposed.

Abstract translation: 提供了一种在PCB的底表面上具有模制球的半导体封装以及半导体封装的制造方法。 所述半导体封装包括：半导体芯片安装构件，其包括在第一表面上的电路图案，绝缘层限定露出所述电路图案的至少一部分的开口以及布置在由所述开口暴露的所述电路图案部分上的外部接触端子; 半导体芯片，形成在所述半导体芯片安装构件的第二表面上并电连接到所述半导体芯片安装构件; 涂覆半导体芯片安装构件和半导体芯片的第二表面的第一密封部分; 以及布置在绝缘层和外部接触端子上的第二密封部分，使得外部接触端子的至少一部分露出。

公开(公告)号：US20080054462A1

公开(公告)日：2008-03-06

申请号：US11850576

申请日：2007-09-05

Applicant: Young-Lyong KIM ,  Young-Shin CHOI ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Chul-Yong JANG ,  Hyun-Jong WOO

Inventor： Young-Lyong KIM ,  Young-Shin CHOI ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Chul-Yong JANG ,  Hyun-Jong WOO

IPC: H01L23/52 ,  H01R12/00 ,  H05K3/00

CPC classification number: H05K3/4084 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/38 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/09481 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/0195 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract translation: 提供了具有提高互连层之间的可靠性的凸块互连结构的印刷电路板。 还提供了使用印刷电路板制造印刷电路板和半导体封装的方法。 根据一个实施例，印刷电路板包括形成在第一互连层和第二互连层之间的树脂层上的多个凸点。 第二互连层包括对应于凸起的上部的插入孔，使得凸起的上部从第二互连层突出。 至少一个凸块的上部包括具有大于相应插入孔的直径的直径的铆钉部分，以可靠地互连第一和第二互连层。