公开(公告)号：US20120007227A1

公开(公告)日：2012-01-12

申请号：US13162846

申请日：2011-06-17

申请人： Yun-Rae CHO ,  Kun-Dae Yeom

发明人： Yun-Rae CHO ,  Kun-Dae Yeom

IPC分类号： H01L25/11 ,  H01L25/07

CPC分类号： H01L25/03 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32151 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

摘要翻译： 一种半导体封装，包括保护层，堆叠在保护层上的多个半导体芯片，设置在保护层上以包围半导体芯片的侧表面的内部密封剂，以及被设置成埋入内部的上部的端子 密封剂。 这里，每个半导体芯片包括有源表面，与有源表面相对的无效表面和设置在有源表面的一部分上的芯片焊盘，并且端子的上表面从内表面的上表面露出 密封剂。

公开(公告)号：US07521289B2

公开(公告)日：2009-04-21

申请号：US11213702

申请日：2005-08-30

申请人： Young-min Lee ,  Kun-dae Yeom

发明人： Young-min Lee ,  Kun-dae Yeom

IPC分类号： H01L21/44

CPC分类号： H01L23/562 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package may include a stack of unit chip packages, and each unit chip package may include a printed circuit board. The printed circuit board may support a semiconductor chip and a connection terminal for connecting to an adjacent unit chip package within the stack. A dummy package substrate may be disposed on the semiconductor chip of the uppermost unit chip package for protecting the semiconductor chip of the uppermost unit chip package. A method of fabricating a package may involve stacking unit chip packages so that the printed circuit board of a lower unit chip package abuts against a solder bump of an upper unit chip package, and stacking a dummy package substrate on the printed circuit board of an uppermost unit chip package.

摘要翻译： 封装可以包括单元芯片封装的堆叠，并且每个单元芯片封装可以包括印刷电路板。 印刷电路板可以支撑半导体芯片和用于连接到堆叠内的相邻单元芯片封装的连接端子。 可以在最上面的单元芯片封装的半导体芯片上设置虚拟封装衬底，以保护最上面的单元芯片封装的半导体芯片。 制造封装的方法可以包括堆叠单元芯片封装，使得下单元芯片封装的印刷电路板与上单元芯片封装的焊料凸块抵接，并将虚拟封装衬底堆叠在最上层的印刷电路板上 单元芯片封装。

公开(公告)号：US20080054462A1

公开(公告)日：2008-03-06

申请号：US11850576

申请日：2007-09-05

申请人： Young-Lyong KIM ,  Young-Shin CHOI ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Chul-Yong JANG ,  Hyun-Jong WOO

发明人： Young-Lyong KIM ,  Young-Shin CHOI ,  Jong-Gi LEE ,  Kun-Dae YEOM ,  Chul-Yong JANG ,  Hyun-Jong WOO

IPC分类号： H01L23/52 ,  H01R12/00 ,  H05K3/00

CPC分类号： H05K3/4084 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/38 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/09481 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/0195 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2224/0401

摘要： Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

摘要翻译： 提供了具有提高互连层之间的可靠性的凸块互连结构的印刷电路板。 还提供了使用印刷电路板制造印刷电路板和半导体封装的方法。 根据一个实施例，印刷电路板包括形成在第一互连层和第二互连层之间的树脂层上的多个凸点。 第二互连层包括对应于凸起的上部的插入孔，使得凸起的上部从第二互连层突出。 至少一个凸块的上部包括具有大于相应插入孔的直径的直径的铆钉部分，以可靠地互连第一和第二互连层。

公开(公告)号：US20060049501A1

公开(公告)日：2006-03-09

申请号：US11100526

申请日：2005-04-07

申请人： Young-min Lee ,  Kun-dae Yeom

发明人： Young-min Lee ,  Kun-dae Yeom

IPC分类号： H01L23/02

CPC分类号： H01L23/562 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package may include a stack of unit chip packages, and each unit chip package may include a printed circuit board. The printed circuit board may support a semiconductor chip and a connection terminal for connecting to an adjacent unit chip package within the stack. A dummy package substrate may be disposed on the semiconductor chip of the uppermost unit chip package for protecting the semiconductor chip of the uppermost unit chip package. A method of fabricating a package may involve stacking unit chip packages so that the printed circuit board of a lower unit chip package abuts against a solder bump of an upper unit chip package, and stacking a dummy package substrate on the printed circuit board of an uppermost unit chip package.

公开(公告)号：US08664757B2

公开(公告)日：2014-03-04

申请号：US13162846

申请日：2011-06-17

申请人： Yun-Rae Cho ,  Kun-Dae Yeom

发明人： Yun-Rae Cho ,  Kun-Dae Yeom

IPC分类号： H01L29/66

CPC分类号： H01L25/03 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32151 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

摘要翻译： 一种半导体封装，包括保护层，堆叠在保护层上的多个半导体芯片，设置在保护层上以包围半导体芯片的侧表面的内部密封剂，以及被设置成埋入内部的上部的端子 密封剂。 这里，每个半导体芯片包括有源表面，与有源表面相对的无效表面和设置在有源表面的一部分上的芯片焊盘，并且端子的上表面从内表面的上表面露出 密封剂。

公开(公告)号：US20120217656A1

公开(公告)日：2012-08-30

申请号：US13465387

申请日：2012-05-07

申请人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

发明人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC分类号： H01L23/52

CPC分类号： H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

摘要翻译： 提供了包括多个半导体芯片的半导体封装以及连接到半导体芯片的分离的引线组。 引线暴露于半导体封装的外部。 多个引线可以包括用于第一芯片组的第一引线组和用于第二芯片组的第二引线组。 第一和第二芯片组是封装的一部分。

公开(公告)号：US08193626B2

公开(公告)日：2012-06-05

申请号：US12630363

申请日：2009-12-03

申请人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

发明人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC分类号： H01L23/02

CPC分类号： H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

摘要翻译： 提供了包括多个半导体芯片的半导体封装以及连接到半导体芯片的分离的引线组。 引线暴露于半导体封装的外部。 多个引线可以包括用于第一芯片组的第一引线组和用于第二芯片组的第二引线组。 第一和第二芯片组是封装的一部分。

公开(公告)号：US20110304056A1

公开(公告)日：2011-12-15

申请号：US13158722

申请日：2011-06-13

申请人： Dong-hun Lee ,  Hyung-gil Baek ,  Kun-dae Yeom

发明人： Dong-hun Lee ,  Hyung-gil Baek ,  Kun-dae Yeom

IPC分类号： H01L23/48

CPC分类号： H01L25/03 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45139 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01049

摘要： A stack-type semiconductor package includes: a substrate; a first through electrode module stacked on the substrate comprising a first chip and a second chip connected to the first chip by a first through electrode; a second through electrode module stacked on the first through electrode comprising a third chip and a fourth chip connected to the third chip by a second through electrode; and a signal transmission medium for electrically connecting the substrate to the first through electrode module and the second through electrode module. The stack-type semiconductor package may be highly integrated, reliability thereof is improved by increasing strength of the chips, stacking in high-steps is possible, the stack-type semiconductor package may be thin and simple, and productivity thereof may be significantly increased.

摘要翻译： 堆叠型半导体封装包括：衬底; 堆叠在所述基板上的第一贯通电极模块，包括通过第一贯通电极连接到所述第一芯片的第一芯片和第二芯片; 堆叠在第一贯通电极上的第二贯通电极模块，包括通过第二贯通电极连接到第三芯片的第三芯片和第四芯片; 以及用于将基板电连接到第一贯通电极模块和第二贯通电极模块的信号传输介质。 堆叠型半导体封装可以高度集成，通过提高芯片的强度来提高其可靠性，可以堆叠高阶层叠，堆叠型半导体封装可以是薄且简单的，并且其生产率可以显着增加。

公开(公告)号：US20100117217A1

公开(公告)日：2010-05-13

申请号：US12630363

申请日：2009-12-03

申请人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

发明人： Chul Park ,  Hysong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

摘要翻译： 提供了包括多个半导体芯片的半导体封装以及连接到半导体芯片的分离的引线组。 引线暴露于半导体封装的外部。 多个引线可以包括用于第一芯片组的第一引线组和用于第二芯片组的第二引线组。 第一和第二芯片组是封装的一部分。

公开(公告)号：US20080122081A1

公开(公告)日：2008-05-29

申请号：US11902260

申请日：2007-09-20

申请人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Eun-Chul Ahn

发明人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Eun-Chul Ahn

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H05K1/02 ,  H01L23/498 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H05K1/09 ,  H05K3/0052 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0391 ,  H05K2201/09781 ,  H05K2203/0315 ,  H05K2203/175

摘要： According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on the substrate. A sacrificial pattern electrically connected to the metal interconnection and serving as a sacrificial anode for cathodic protection against corrosion of the metal interconnection may be formed on the second area. An opening to expose the metal interconnection on the first area may be formed by patterning the insulating layer. An electronic device fabricated by a method according to an example embodiment may include a substrate, a metal interconnection, an insulating layer, and/or a sacrificial pattern.

摘要翻译： 根据示例性实施例，制造电子设备的方法可以包括制备具有第一区域和第二区域的基板。 可以在从第一区域延伸到第二区域的基板上形成金属互连。 可以在基板上形成绝缘层。 电连接到金属互连并用作用于阴极保护以防止金属互连的腐蚀的牺牲阳极的牺牲图案可以形成在第二区域上。 可以通过图案化绝缘层来形成用于暴露第一区域上的金属互连的开口。 通过根据示例实施例的方法制造的电子器件可以包括衬底，金属互连，绝缘层和/或牺牲图案。