公开(公告)号：US20110318876A1

公开(公告)日：2011-12-29

申请号：US13041422

申请日：2011-03-06

申请人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

发明人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

IPC分类号： H01L21/60 ,  H01L21/56

CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

摘要翻译： 在一个实施例中，半导体封装可以包括：半导体芯片，其具有形成在其第一表面上的芯片焊盘，用于密封半导体芯片并暴露半导体芯片的第一表面的密封构件，覆盖第一 并且直接接触密封部件的上表面的一部分。 导电布线还接触垫。 半导体封装还可以包括覆盖导电布线并具有露出导电布线部分的开口的密封剂。

公开(公告)号：US08664762B2

公开(公告)日：2014-03-04

申请号：US13594841

申请日：2012-08-26

申请人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

发明人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

IPC分类号： H01L23/48

CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

摘要翻译： 在一个实施例中，半导体封装可以包括：半导体芯片，其具有形成在其第一表面上的芯片焊盘，用于密封半导体芯片并暴露半导体芯片的第一表面的密封构件，覆盖第一 并且直接接触密封部件的上表面的一部分。 导电布线还接触垫。 半导体封装还可以包括覆盖导电布线并具有露出导电布线部分的开口的密封剂。

公开(公告)号：US20120313244A1

公开(公告)日：2012-12-13

申请号：US13594841

申请日：2012-08-26

申请人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

发明人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

IPC分类号： H01L23/498

CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

摘要翻译： 在一个实施例中，半导体封装可以包括：半导体芯片，其具有形成在其第一表面上的芯片焊盘，用于密封半导体芯片并暴露半导体芯片的第一表面的密封构件，覆盖第一 并且直接接触密封部件的上表面的一部分。 导电布线还接触垫。 半导体封装还可以包括覆盖导电布线并具有露出导电布线部分的开口的密封剂。

公开(公告)号：US08288210B2

公开(公告)日：2012-10-16

申请号：US13041422

申请日：2011-03-06

申请人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

发明人： Jong-gi Lee ,  Sang-wook Park ,  Ji-seok Hong

IPC分类号： H01L21/00

CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

摘要翻译： 在一个实施例中，半导体封装可以包括：半导体芯片，其具有形成在其第一表面上的芯片焊盘，用于密封半导体芯片并暴露半导体芯片的第一表面的密封构件，覆盖第一 并且直接接触密封部件的上表面的一部分。 导电布线还接触垫。 半导体封装还可以包括覆盖导电布线并具有露出导电布线部分的开口的密封剂。

公开(公告)号：US20100144137A1

公开(公告)日：2010-06-10

申请号：US12579483

申请日：2009-10-15

申请人： Kwang-yong LEE ,  Jong-gi Lee ,  Min-ill Kim ,  Min-seung Yoon ,  Ji-seok Hong

发明人： Kwang-yong LEE ,  Jong-gi Lee ,  Min-ill Kim ,  Min-seung Yoon ,  Ji-seok Hong

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/81097 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method of interconnecting semiconductor devices by using capillary motion, thereby simplifying fabricating operations, reducing fabricating costs, and simultaneously filling of through-silicon-vias (TSVs) and interconnecting semiconductor devices. The method includes preparing a first semiconductor device in which first TSVs are formed, positioning solder balls respectively on the first TSVs, performing a back-lap operation on the first semiconductor device, positioning a second semiconductor device, in which second TSVs are formed, above the first semiconductor device on which the solder balls are positioned, and performing a reflow operation such that the solder balls fill the first and second TSVs due to capillary motion.

摘要翻译： 通过使用毛细管运动来互连半导体器件的方法，从而简化了制造操作，降低了制造成本，同时填充了通过硅通孔（TSV）和互连半导体器件。 该方法包括制备其中形成第一TSV的第一半导体器件，分别将焊球定位在第一TSV上，在第一半导体器件上执行回搭操作，将形成有第二TSV的第二半导体器件定位在其中，形成第二TSV 焊球位于其上的第一半导体器件，并且执行回流操作，使得焊球由于毛细管运动而填充第一和第二TSV。

公开(公告)号：US20150130078A1

公开(公告)日：2015-05-14

申请号：US14499591

申请日：2014-09-29

申请人： Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

发明人： Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/367 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member disposed on the top surface of the first package.

摘要翻译： POP结构的半导体封装包括第一和第二半导体封装，第二半导体封装直接安装在第一和第二半导体封装上，并且包含多个半导体芯片。 第二封装中的芯片经由贯通电极电连接，第一和第二封装通过布置在第一封装的顶表面上的连接构件连接。

公开(公告)号：US20140084456A1

公开(公告)日：2014-03-27

申请号：US13774209

申请日：2013-02-22

申请人： Myun-sung Kang ,  Jung-min Ko ,  Sang-sick Park ,  Won-keun Kim ,  Ji-seok Hong

发明人： Myun-sung Kang ,  Jung-min Ko ,  Sang-sick Park ,  Won-keun Kim ,  Ji-seok Hong

IPC分类号： H01L23/28 ,  H01L23/498

CPC分类号： H01L23/28 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers.

摘要翻译： 半导体封装包括第一半导体芯片，第一半导体芯片上的第二半导体芯片，第二半导体芯片上的第三半导体芯片和第三半导体芯片上的第四半导体芯片。 第一底部填充层位于第二半导体芯片和第一半导体芯片之间; 第二底部填充层位于第三半导体芯片和第二半导体芯片之间，第三底层填充层位于第四半导体芯片和第三半导体芯片之间。 在一些实施例中，第二底部填充层包括不同于第一和第三底部填充层的材料。