公开(公告)号：US20100181887A1

公开(公告)日：2010-07-22

申请号：US12691156

申请日：2010-01-21

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01J1/02

CPC classification number: H01L33/647 ,  G02B6/0023 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/01066 ,  H01L2924/00014

Abstract: A light emitting device with improved heat dissipation is provided. The light emitting device includes a first lead frame, a second lead frame, a light emitting element and a housing. The first lead frame includes a light emitting element mounting portion, a first heat dissipation portion extending from the light emitting element mounting portion in a first direction, and second and third heat dissipation portions extending from the light emitting element mounting portion in a second direction opposite to the first direction. The second lead frame extends in the second direction and is disposed between and spaced apart from the second and third heat dissipation portions. The light emitting element is mounted on the light emitting element mounting portion and is electrically coupled to the first and second lead frames. The housing encapsulates the first and second lead frames. The second and third heat dissipation portions have a first width and the second lead frame has a second width the same as or different from the first width.

Abstract translation: 提供了具有改善的散热的发光装置。 发光器件包括第一引线框架，第二引线框架，发光元件和壳体。 第一引线框架包括发光元件安装部分，从第一方向从发光元件安装部分延伸的第一散热部分和从发光元件安装部分沿相反的第二方向延伸的第二和第三散热部分 到第一个方向。 第二引线框架沿第二方向延伸并且设置在第二和第三散热部分之间并与第二和第三散热部分间隔开。 发光元件安装在发光元件安装部分上并且电耦合到第一引线框架和第二引线框架。 壳体封装第一和第二引线框架。 第二和第三散热部分具有第一宽度，第二引线框架具有与第一宽度相同或不同的第二宽度。

公开(公告)号：US20070252271A1

公开(公告)日：2007-11-01

申请号：US11740821

申请日：2007-04-26

Applicant: Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

IPC: H01L23/34

CPC classification number: H01L25/16 ,  G11C5/04 ,  H01L21/563 ,  H01L25/0655 ,  H01L2224/73203 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract translation: 提供了一种半导体存储器模块，其允许形成在模块基板和安装在模块基板上的存储芯片之间的填充构件完全填充模块基板和存储器芯片之间的空间。 根据本发明的实施例，半导体存储器模块包括具有安装在基板上的至少一个存储芯片的模块基板，使得其边缘对于将模块基板平分的主轴和短轴倾斜。 倾斜方向允许在基板上形成的存储芯片之间的开口改善，使得填充构件可以适当地形成在模块基板和存储芯片之间，以防止填充构件未形成的空隙。

公开(公告)号：US20090057880A1

公开(公告)日：2009-03-05

申请号：US12136608

申请日：2008-06-10

Applicant: Joong-Hyun BAEK ,  Sung-Jun IM

Inventor： Joong-Hyun BAEK ,  Sung-Jun IM

IPC: H01L23/488

CPC classification number: H01L23/522 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/585 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  Y10S438/926 ,  H01L2224/05599

Abstract: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices.

Abstract translation: 一种半导体器件，能够提高通过虚拟焊盘分散热的效率。 半导体器件可以包括在半导体封装，堆叠模块，卡或系统中。 还公开了一种制造半导体器件的方法。 在半导体器件中，半导体衬底具有与第一表面相对的第一表面和第二表面，并且至少一个导电焊盘被布置在第一表面的预定区域上。 至少一个虚拟焊盘布置在第一或第二表面上，并且不电耦合到至少一个导电焊盘。 虚拟垫或垫可用于分散热量。 因此，可以提高半导体器件的分散效率，从而提高半导体器件的产量。

公开(公告)号：US20080099909A1

公开(公告)日：2008-05-01

申请号：US11927457

申请日：2007-10-29

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L23/34 ,  H01L21/58

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 以及填充冷却通孔内部的冷却剂。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20120001348A1

公开(公告)日：2012-01-05

申请号：US13235850

申请日：2011-09-19

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L23/46

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并被密封; 形成在冷却通孔圆周上的微孔; 并且冷却剂填充在冷却通孔的内部。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20100079966A1

公开(公告)日：2010-04-01

申请号：US12564073

申请日：2009-09-22

Applicant: Joong-Hyun BAEK

Inventor： Joong-Hyun BAEK

IPC: H01L25/16 ,  H05K7/06

CPC classification number: G11C5/04 ,  G06F11/1044 ,  G11C5/02 ,  G11C5/025 ,  G11C2029/0411 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A memory module includes a printed circuit board (PCB), and a plurality of semiconductor packages and a multi-functional package mounted to the PCB. The multi-functional package may have a data processing function and an error correcting function. Thus, the packages may occupy a relatively small area of the PCB in terms of the number of functions that they provide. Thus, the module may be highly integrated.

Abstract translation: 存储器模块包括印刷电路板（PCB）和多个半导体封装以及安装到PCB的多功能封装。 多功能包可具有数据处理功能和纠错功能。 因此，根据它们提供的功能的数量，封装可占据PCB的相对小的面积。 因此，该模块可以高度集成。

公开(公告)号：US20070252257A1

公开(公告)日：2007-11-01

申请号：US11741623

申请日：2007-04-27

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE ,  Hae-Hyung LEE ,  Sun-Won KANG

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE ,  Hae-Hyung LEE ,  Sun-Won KANG

IPC: H01L23/02

CPC classification number: H01L23/3675 ,  H01L23/36 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a semiconductor package structure includes a heat dissipative element connected to an internal circuit. The semiconductor package includes a semiconductor chip, an interconnection substrate, and a heat dissipative element. The semiconductor chip includes an internal circuit and inner pads that connect the internal circuit. The interconnection substrate is disposed below the semiconductor chip and includes input/output terminals. At least one of the inner pads is electrically connected to at least one of the input/output terminals. The heat dissipative element is disposed on the semiconductor chip and is electrically connected to at least one of the inner pads.

Abstract translation: 在一个实施例中，半导体封装结构包括连接到内部电路的散热元件。 半导体封装包括半导体芯片，互连衬底和散热元件。 半导体芯片包括连接内部电路的内部电路和内部焊盘。 互连基板设置在半导体芯片的下方并且包括输入/​​输出端子。 内部焊盘中的至少一个电连接到至少一个输入/输出端子。 散热元件设置在半导体芯片上并与至少一个内部焊盘电连接。

公开(公告)号：US20100059880A1

公开(公告)日：2010-03-11

申请号：US12554173

申请日：2009-09-04

Applicant: Joong-Hyun BAEK

Inventor： Joong-Hyun BAEK

IPC: H01L23/34

CPC classification number: H01L23/467 ,  H01L23/5385 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/144 ,  H05K1/147 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/046 ,  H05K2201/056 ,  H05K2201/10159 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module.

Abstract translation: 提供了三维半导体模块和包括该三维半导体模块的电子系统。 半导体模块包括模块衬底，形成在模块衬底的一部分上的逻辑器件和形成在模块衬底的另一部分上的多个存储器件，其中多个存储器件垂直于逻辑器件设置，以及 其上形成有多个存储器件的模块衬底由支撑件支撑。 电子系统包括半导体模块。

公开(公告)号：US20100038769A1

公开(公告)日：2010-02-18

申请号：US12581920

申请日：2009-10-20

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L25/065

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 并且冷却剂填充在冷却通孔的内部。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20090186404A1

公开(公告)日：2009-07-23

申请号：US12333113

申请日：2008-12-11

Applicant: Jae-Young KIM ,  Joong-Hyun BAEK

Inventor： Jae-Young KIM ,  Joong-Hyun BAEK

IPC: C12M1/00

CPC classification number: B01L7/525 ,  B01L3/5027 ,  B01L3/502707 ,  B01L2300/0816 ,  B01L2300/087 ,  B01L2300/1822 ,  B01L2300/1827 ,  B01L2400/0487

Abstract: Provided is a nucleic acid amplifying apparatus having a uniform distribution of reaction temperature in a reaction space. The nucleic acid amplifying apparatus includes a substrate providing a polymerase chain reaction (PCR) space, and a plurality of heating units disposed above or below the reaction space to transfer heat to the reaction space, wherein the heating unit includes a plurality of heating units arranged substantially in parallel with each other, and among the plurality of heating units, the heating units disposed adjacent outermost portions of the reaction space have the largest heat radiation quantity.

Abstract translation: 提供了在反应空间中具有均匀的反应温度分布的核酸扩增装置。 核酸扩增装置包括提供聚合酶链反应（PCR）空间的基板和设置在反应空间上方或下方的多个加热单元，以将热量传递到反应空间，其中加热单元包括多个加热单元，其布置 基本上彼此平行，并且在多个加热单元中，邻近反应空间的最外部设置的加热单元具有最大的散热量。