公开(公告)号：US20120073861A1

公开(公告)日：2012-03-29

申请号：US13235110

申请日：2011-09-16

申请人： Ju-Pyo HONG ,  Young-Do Kweon ,  Jin-Gu Kim ,  Seon-Hee Moon ,  Dong-Jin Lee ,  Seung-Wook Park

发明人： Ju-Pyo HONG ,  Young-Do Kweon ,  Jin-Gu Kim ,  Seon-Hee Moon ,  Dong-Jin Lee ,  Seung-Wook Park

IPC分类号： H05K1/02 ,  H05K3/10

CPC分类号： H05K3/4644 ,  H05K1/0271 ,  H05K2201/09036

摘要： A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.

摘要翻译： 公开了印刷电路板和印刷电路板的制造方法。 印刷电路板包括：第一绝缘层，其上形成有第一图案; 沿着所述第一图案的至少一部分在所述第一绝缘层的一个表面中凹陷的第一沟槽; 以及层叠在所述第一绝缘层的一个表面上以覆盖所述第一图案的第二绝缘层。 第一沟槽由第二绝缘层填充。

公开(公告)号：US08624128B2

公开(公告)日：2014-01-07

申请号：US13235110

申请日：2011-09-16

申请人： Ju-Pyo Hong ,  Young-Do Kweon ,  Jin-Gu Kim ,  Seon-Hee Moon ,  Dong-Jin Lee ,  Seung-Wook Park

发明人： Ju-Pyo Hong ,  Young-Do Kweon ,  Jin-Gu Kim ,  Seon-Hee Moon ,  Dong-Jin Lee ,  Seung-Wook Park

IPC分类号： H05K1/02

CPC分类号： H05K3/4644 ,  H05K1/0271 ,  H05K2201/09036

摘要： A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.

摘要翻译： 公开了印刷电路板和印刷电路板的制造方法。 印刷电路板包括：第一绝缘层，其上形成有第一图案; 沿着所述第一图案的至少一部分在所述第一绝缘层的一个表面中凹陷的第一沟槽; 以及层叠在第一绝缘层的一个表面上以覆盖第一图案的第二绝缘层。 第一沟槽由第二绝缘层填充。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

公开(公告)号：US20090253259A1

公开(公告)日：2009-10-08

申请号：US12222967

申请日：2008-08-20

申请人： Jingli Yuan ,  Young-Do Kweon ,  Jae-Kwang Lee ,  Jong-Hwan Baek ,  Hyung-Jin Jeon ,  Seung-Wook Park

发明人： Jingli Yuan ,  Young-Do Kweon ,  Jae-Kwang Lee ,  Jong-Hwan Baek ,  Hyung-Jin Jeon ,  Seung-Wook Park

IPC分类号： H01L21/60 ,  B23K37/04

CPC分类号： B23K1/0016 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014

摘要： Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes.

摘要翻译： 公开了焊接附着夹具和使用其的半导体器件的制造方法。 布置焊球与半导体晶片的导电柱对准的焊球附着夹具可以包括主体和容纳孔，其形成在主体上以保持焊球。 相互面对的接收孔的内壁对称地倾斜。 使用根据本发明的实施例的焊球附着夹具，可以提高焊球的对准，同时降低成本并简化工艺。

公开(公告)号：US20090087951A1

公开(公告)日：2009-04-02

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/02

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

摘要翻译： 公开了一种制造晶片级封装的方法。 该方法可以包括在晶片衬底上堆叠绝缘层; 处理绝缘层中的通孔; 在所述绝缘层上形成种子层; 在种子层上形成与再分布图案对应关系的电镀抗蚀剂; 通过电镀形成包括用于外部接触的端子的再分布图案; 并将导电球耦合到端子。 由于可以使用廉价的PCB工艺形成多个再分布层，所以可以降低制造成本，并且可以提高工艺的稳定性和效率。

公开(公告)号：US08064215B2

公开(公告)日：2011-11-22

申请号：US12230872

申请日：2008-09-05

申请人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

发明人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC分类号： H05K1/18

CPC分类号： H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

摘要翻译： 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。

公开(公告)号：US20090073667A1

公开(公告)日：2009-03-19

申请号：US12230872

申请日：2008-09-05

申请人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

发明人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC分类号： H05K1/18 ,  H01L27/06

CPC分类号： H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

摘要翻译： 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。

公开(公告)号：US20100084754A1

公开(公告)日：2010-04-08

申请号：US12591792

申请日：2009-12-01

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

IPC分类号： H01L25/065

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate.

摘要翻译： 一种半导体封装，其包括在其上形成有预先设计的图案的第一基板; 通过倒装芯片方法在所述第一基板的一侧上安装的第一芯片; 在所述第一基板的边缘上形成为预定厚度的支撑件; 插入器，其具有放置在支撑体上的边缘，使得所述插入件覆盖所述第一基板并在所述插入件与所述第一基板之间形成空腔，并且具有分别形成在其两侧的预先设计的图案; 穿过支撑件和插入件的通孔; 第二芯片，安装在所述插入器的面向所述第一基板的一侧上; 放置在所述插入件的另一侧上的第二衬底，其中至少一个导电球定位在其间; 以及安装在所述第二基板上的第三芯片。

公开(公告)号：US20100087035A1

公开(公告)日：2010-04-08

申请号：US12591791

申请日：2009-12-01

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Bum-Sik Jang ,  Tae-Sung Jeong

IPC分类号： H01L21/60

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.

摘要翻译： 一种制造半导体封装的方法，包括通过倒装芯片方法将第一芯片安装在第一衬底上，所述第一衬底在其上形成预先设计的图案; 在与形成在第一基板上的图案电连接的至少一个预定位置上进行焊接而形成至少一个凸块; 通过进行模制来形成第一模制件，使得第一模塑件覆盖第一基板和第一芯片; 在第一次成型时放置插入件; 以及将第二衬底放置在所述插入件上，所述第二衬底具有安装在其上的第二芯片。

公开(公告)号：US20090244864A1

公开(公告)日：2009-10-01

申请号：US12320794

申请日：2009-02-04

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H05K1/18 ,  B32B7/00 ,  B32B37/02

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： Disclosed are a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof. The capacitor-embedded printed circuit board can include a core board, an insulation resin layer, which is stacked on the core board, a first electrode and a first circuit pattern, which are buried in the insulation resin layer, a dielectric layer, which is stacked on a surface of the insulation resin layer, a first adhesive resin layer, which is stacked on the dielectric layer, and a second electrode and a second circuit pattern, which are formed on a surface of the first adhesive resin layer to correspond with the first electrode. With the present invention, the manufacturing process can be simplified and the reliability of products can be improved by reducing the variation of the capacitor (C).

摘要翻译： 公开了用于电容器嵌入式印刷电路板的基板，电容器嵌入式印刷电路板及其制造方法。 电容器嵌入式印刷电路板可以包括堆叠在芯板上的芯板，绝缘树脂层，埋在绝缘树脂层中的第一电极和第一电路图案，介电层，其是 堆叠在绝缘树脂层的表面上，堆叠在电介质层上的第一粘合树脂层和形成在第一粘合树脂层的表面上的第二电极和第二电路图案，以对应于 第一电极。 利用本发明，可以简化制造工艺，并且可以通过减小电容器（C）的变化来提高产品的可靠性。