公开(公告)号：US07884454B2

公开(公告)日：2011-02-08

申请号：US12209106

申请日：2008-09-11

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/495

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

公开(公告)号：US20090008758A1

公开(公告)日：2009-01-08

申请号：US12209106

申请日：2008-09-11

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/495 ,  H01L21/58 ,  H01L23/488

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

摘要翻译： 半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。 垂直半导体器件可以结合到芯片焊盘。 该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。 电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。 导电迹线在第一接合线和第二接合线之间提供导电路径。 导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

公开(公告)号：US08049315B2

公开(公告)日：2011-11-01

申请号：US13007279

申请日：2011-01-14

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Kenny Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Kenny Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/495

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

摘要翻译： 半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。 垂直半导体器件可以结合到芯片焊盘。 该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。 电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。 导电迹线在第一接合线和第二接合线之间提供导电路径。 导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

公开(公告)号：US20110108998A1

公开(公告)日：2011-05-12

申请号：US13007279

申请日：2011-01-14

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/52

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

摘要翻译： 半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。 垂直半导体器件可以结合到芯片焊盘。 该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。 电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。 导电迹线在第一接合线和第二接合线之间提供导电路径。 导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

公开(公告)号：US08581376B2

公开(公告)日：2013-11-12

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L21/44 ,  H01L21/31

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20110227207A1

公开(公告)日：2011-09-22

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L23/52 ,  H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US09478646B2

公开(公告)日：2016-10-25

申请号：US13192385

申请日：2011-07-27

申请人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

发明人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

摘要翻译： 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US20090057869A1

公开(公告)日：2009-03-05

申请号：US11849160

申请日：2007-08-31

申请人： Francois Hebert ,  Xiaotian Zhang ,  Kai Liu ,  Ming Sun ,  Anup Bhalla

发明人： Francois Hebert ,  Xiaotian Zhang ,  Kai Liu ,  Ming Sun ,  Anup Bhalla

IPC分类号： H01L23/52

CPC分类号： H01L24/41 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L25/072 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01055 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/37099 ,  H01L2924/206

摘要： A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.

摘要翻译： 公开了电路封装组件。 组件包括导电基板; 具有在与导电基板的表面相对并与其电接触的一侧具有源极的高边n沟道金属氧化物半导体场效应晶体管（NMOSFET）和低侧标准n沟道金属氧化物半导体场效应晶体管（ NMOSFET），其在面向导电基板的一侧具有漏极并与其电接触。 与传统封装相比，以这种方式共同封装高边和低边NMOSFET可以减小封装尺寸和寄生电感和电容。

公开(公告)号：US20140374823A1

公开(公告)日：2014-12-25

申请号：US13925776

申请日：2013-06-24

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L29/78

CPC分类号： H01L29/7803 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US08802530B2

公开(公告)日：2014-08-12

申请号：US13490138

申请日：2012-06-06

申请人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/42

CPC分类号： H01L29/7813 ,  H01L21/42 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734

摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。 在底部绝缘体上方的沟槽中形成导电栅电极。 栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。 在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。