公开(公告)号：US20150054099A1

公开(公告)日：2015-02-26

申请号：US13975359

申请日：2013-08-25

申请人： Kai Yun Yow ,  Poh Leng Eu ,  Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Kai Yun Yow ,  Poh Leng Eu ,  Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L29/84 ,  H01L25/00 ,  H01L21/56 ,  H01L25/18

CPC分类号： H01L21/56 ,  G01L19/147 ,  H01L21/50 ,  H01L23/24 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2924/16315 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/0665

摘要： A semiconductor sensor device is assembled using a pre-molded lead frame having first and second die flags. The first die flag includes a cavity. A pressure sensor die (P-cell) is mounted within the cavity and a master control unit die (MCU) is mounted to the second flag. The P-cell and MCU are electrically connected to leads of the lead frame with bond wires. The die attach and wire bonding steps are each done in a single pass. A mold pin is placed over the P-cell and then the MCU is encapsulated with a mold compound. The mold pin is removed leaving a recess that is next filled with a gel material. Finally a lid is placed over the P-cell and gel material. The lid includes a hole that that exposes the gel-covered active region of the pressure sensor die to ambient atmospheric pressure outside the sensor device.

摘要翻译： 使用具有第一和第二管芯标记的预模制引线框组装半导体传感器装置。 第一个模具标志包括一个空腔。 压力传感器管芯（P-cell）安装在腔内，并且主控单元管芯（MCU）安装到第二标志上。 P单元和MCU通过接合线电连接到引线框架的引线。 芯片连接和引线键合步骤都是单次完成的。 模具销放置在P型电池上，然后用模具化合物封装MCU。 去除模具销，留下下一个填充有凝胶材料的凹槽。 最后将盖子放置在P细胞和凝胶材料上。 盖子包括孔，该孔将压力传感器芯片的凝胶覆盖的有源区域暴露于传感器装置外部的环境大气压力。

公开(公告)号：US09437492B2

公开(公告)日：2016-09-06

申请号：US14499266

申请日：2014-09-29

申请人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

发明人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/83132 ,  H01L2224/85132 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

摘要翻译： 使用替代不同配置的半导体管芯组装半导体器件的方法使用相同的衬底面板。 所选择的配置的管芯被放置在阵列中，安装并连接到面板的第一面上的内部电接触焊盘，使用主要的基准标记和通常对应于不同替代的半导体管芯阵列的辅助基准标记阵列 配置 附属基准标记的间距等于面板上的内部电接触焊盘的相邻行之间的间隔，并且是管芯阵列的间距的次倍数。

公开(公告)号：US20160093533A1

公开(公告)日：2016-03-31

申请号：US14499266

申请日：2014-09-29

申请人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

发明人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L21/78 ,  H01L23/28 ,  H01L23/535 ,  H01L23/544 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/83132 ,  H01L2224/85132 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

摘要翻译： 使用替代不同配置的半导体管芯组装半导体器件的方法使用相同的衬底面板。 所选择的配置的管芯被放置在阵列中，安装并连接到面板的第一面上的内部电接触焊盘，使用主要的基准标记和通常对应于不同替代的半导体管芯阵列的辅助基准标记阵列 配置 附属基准标记的间距等于面板上的内部电接触焊盘的相邻行之间的间隔，并且是管芯阵列的间距的次倍数。

公开(公告)号：US20150183131A1

公开(公告)日：2015-07-02

申请号：US14141471

申请日：2013-12-27

申请人： Chee Seng Foong ,  Wen Shi Koh ,  Kai Yun Yow

发明人： Chee Seng Foong ,  Wen Shi Koh ,  Kai Yun Yow

IPC分类号： B28D5/02 ,  B24D3/06 ,  B24D5/14

CPC分类号： B28D5/022 ,  B24D3/06 ,  B24D5/14

摘要： A dicing blade suitable for cutting a semiconductor wafer has an edge of fine grit for polishing a top surface of the wafer and a protruding part of coarse grit for making an initial cut into the wafer. The blade reduces chipping of the top surface of the wafer and increases throughput by facilitating cutting and polishing in one operation. The blade can dice and polish comparatively thick wafers having narrow scribe lines in a single operation.

摘要翻译： 适用于切割半导体晶片的切割刀片具有用于抛光晶片顶表面的细砂粒边缘和用于初始切割到晶片中的粗砂粒的突出部分。 刀片减少了晶片顶表面的碎裂，并且通过在一次操作中促进切割和抛光来增加产量。 刀片可以在单次操作中骰子和抛光具有窄划线的比较厚的晶片。

公开(公告)号：US08415779B2

公开(公告)日：2013-04-09

申请号：US13047803

申请日：2011-03-15

申请人： Tzu Ling Wong ,  Chee Seng Foong ,  Kai Yun Yow

发明人： Tzu Ling Wong ,  Chee Seng Foong ,  Kai Yun Yow

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49572 ,  H01L24/17 ,  H01L2224/16245 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.

摘要翻译： 用于提供与集成电路（IC）裸片的电互连的引线框架。 引线框架包括用于接收和支撑IC芯片的模具支撑区域和围绕模具支撑区域的多个引线。 在模具支撑区域中形成多个互连接收部分。 互连接收部分用于提供与IC芯片的底表面上的第一凸块的电互连。 引线用于提供与IC芯片的表面上的第二凸块的电互连，第二凸块围绕第一凸块。

公开(公告)号：US20160064356A1

公开(公告)日：2016-03-03

申请号：US14474294

申请日：2014-09-01

申请人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/03602 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L21/565 ,  H01L21/304 ,  H01L2224/83

摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。

公开(公告)号：US09202770B1

公开(公告)日：2015-12-01

申请号：US14474291

申请日：2014-09-01

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/367 ,  H01L21/56 ,  B29B9/12

CPC分类号： H01L23/3675 ,  B29B9/12 ,  B29C45/02 ,  B29C45/14655 ,  B29C45/1634 ,  B29C45/1671 ,  B29C45/462 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A packaged semiconductor device has an integrated circuit (IC) die and first and second volumes of molding compound. The first volume of molding compound is disposed on a first portion of a first side of the IC die and comprises a first molding compound. The second volume of molding compound is disposed on a second side of the IC die, different from the first side, and comprises a second molding compound, different from the first molding compound. By including different molding compounds, the properties of the packaged semiconductor device can be varied across the device.

摘要翻译： 封装的半导体器件具有集成电路（IC）模具和第一和第二体积的模塑料。 第一体积的模塑料被设置在IC模头的第一侧的第一部分上并且包括第一模塑料。 第二体积的成型化合物设置在IC模具的与第一侧不同的第二侧上，并且包括与第一模塑料不同的第二模塑料。 通过包括不同的成型化合物，封装的半导体器件的性能可以在整个器件上变化。

公开(公告)号：US20150201489A1

公开(公告)日：2015-07-16

申请号：US14151828

申请日：2014-01-10

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

CPC分类号： H05K3/007 ,  H05K1/097 ,  H05K2203/107

摘要： A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

摘要翻译： 电路互连衬底制造方法包括在载体的顶部上沉积第一层金属粉末，然后从第一层金属粉末形成第一层导电迹线。 然后将第二层金属粉末沉积到第一层导电迹线的至少一个区域上。 然后从第二层金属粉末形成第二层导电迹线，并且第二层的每个迹线电耦合到第一层的迹线。 将绝缘材料沉积到载体上以提供支撑迹线的绝缘基板。 该方法不需要使用任何湿化学品或化学蚀刻步骤。

公开(公告)号：US20150137354A1

公开(公告)日：2015-05-21

申请号：US14086932

申请日：2013-11-21

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2224/11442 ,  H01L2924/014 ,  H01L2924/00

摘要： A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

摘要翻译： 通过在芯片的表面上的导电焊盘上施加金属粉末，在集成电路芯片上形成诸如铜柱凸起的柱状凸块。 选择性地点燃金属粉末以形成柱状凸块。 任何剩余的非固化金属粉末可以从芯片的表面去除。 可以重复该过程以增加凸起高度。 此外，可以在柱状凸起的外表面上形成焊锡帽。

公开(公告)号：US09474162B2

公开(公告)日：2016-10-18

申请号：US14151828

申请日：2014-01-10

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L21/00 ,  H05K3/00 ,  H05K1/09

CPC分类号： H05K3/007 ,  H05K1/097 ,  H05K2203/107

摘要： A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

摘要翻译： 电路互连衬底制造方法包括在载体的顶部上沉积第一层金属粉末，然后从第一层金属粉末形成第一层导电迹线。 然后将第二层金属粉末沉积到第一层导电迹线的至少一个区域上。 然后从第二层金属粉末形成第二层导电迹线，并且第二层的每个迹线电耦合到第一层的迹线。 将绝缘材料沉积到载体上以提供支撑迹线的绝缘基板。 该方法不需要使用任何湿化学品或化学蚀刻步骤。