公开(公告)号：US20130221499A1

公开(公告)日：2013-08-29

申请号：US13405721

申请日：2012-02-27

申请人： Sampath K.V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sampath K.V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L23/552

CPC分类号： H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/3025

摘要： There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

摘要翻译： 这里公开了位于顶部有源管芯和底部有源管芯之间的屏蔽插入器的各种实现方式，用于屏蔽活动管芯免受电磁噪声。 一种实现方式包括内插器电介质层，内插电介质层内的穿硅通孔（TSV）和电磁屏蔽。 TSV将电磁屏蔽连接到第一固定电位。 电磁屏蔽可以包括横跨屏蔽插入件横向延伸的导电层格。 屏蔽插入器还可以包括连接到另一个固定电位的另一个电磁屏蔽。

公开(公告)号：US20130154106A1

公开(公告)日：2013-06-20

申请号：US13325951

申请日：2011-12-14

申请人： Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Sampath K.V. Karikalan ,  Xiangdong Chen

发明人： Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Sampath K.V. Karikalan ,  Xiangdong Chen

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/78 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

摘要翻译： 本公开的示例性实施方案包括具有来自位于底部重构晶片的底模上方的顶部重构晶片的顶模的堆叠封装。 顶部模具和底部模具通过绝缘装置彼此绝缘。 顶模和底模也通过绝缘装置互连。 绝缘装置可以包括在顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。 顶部模具和底部模具可以通过至少顶部模塑料相互连接。 此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔相互连接。

公开(公告)号：US20130193996A1

公开(公告)日：2013-08-01

申请号：US13362344

申请日：2012-01-31

申请人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： G01R31/26 ,  H01L23/544

CPC分类号： H01L22/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/014

摘要： An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

摘要翻译： 本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。 插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。 至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。 所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

公开(公告)号：US20130168860A1

公开(公告)日：2013-07-04

申请号：US13339234

申请日：2011-12-28

申请人： Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L23/538 ,  H01L23/532

CPC分类号： H01L23/538 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

摘要： There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

摘要翻译： 这里公开了包括没有半导体通孔（TSV）的插入器的半导体封装的各种实施方式。 一个示例性实施方式包括位于中介层之上的第一有源裸片。 插入器包括具有内插器布线迹线的中介层电介质。 第一有源管芯将电信号传送到位于插入器下方的封装衬底，利用内插器布线迹线并且不使用TSV。 在一个实施方案中，半导体封装包括位于插入器上方的第二有源裸片，第二有源裸片利用内插器布线迹线将电信号传送到封装衬底，并且不使用TSV。 此外，在一个实现中，第一有源管芯和第二有源管芯通过插入器传送芯片到芯片信号。

公开(公告)号：US20130168841A1

公开(公告)日：2013-07-04

申请号：US13340430

申请日：2011-12-29

申请人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L23/495 ,  H01L21/326 ,  H05K1/11 ,  B82Y99/00

CPC分类号： H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

摘要翻译： 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

公开(公告)号：US20130181354A1

公开(公告)日：2013-07-18

申请号：US13349045

申请日：2012-01-12

申请人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Xiangdong Chen

发明人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Xiangdong Chen

IPC分类号： H01L23/48

CPC分类号： H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157

摘要： A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

摘要翻译： 半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。 半导体插入器位于衬底上。 插入式管芯设置在半导体插入器的空腔内。 导热粘合剂设置在空腔内并与内插器模具接触。 此外，顶部管芯位于半导体插入器上方。 在一个实现中，半导体插入器是硅插入器。 在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。 在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

公开(公告)号：US09548251B2

公开(公告)日：2017-01-17

申请号：US13349045

申请日：2012-01-12

申请人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

发明人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

IPC分类号： H01L23/48 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157

摘要： A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

摘要翻译： 半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。 半导体插入器位于衬底上。 插入式管芯设置在半导体插入器的空腔内。 导热粘合剂设置在空腔内并与内插器模具接触。 此外，顶部管芯位于半导体插入器上方。 在一个实现中，半导体插入器是硅插入器。 在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。 在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

公开(公告)号：US09041171B2

公开(公告)日：2015-05-26

申请号：US13340430

申请日：2011-12-29

申请人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L21/326 ,  H01L23/495 ,  H05K1/11 ,  B82Y99/00 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/40

CPC分类号： H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

摘要翻译： 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

公开(公告)号：US09153507B2

公开(公告)日：2015-10-06

申请号：US13362344

申请日：2012-01-31

申请人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： G01R31/02 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/014

摘要： An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

摘要翻译： 本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。 插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。 至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。 所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

公开(公告)号：US08791533B2

公开(公告)日：2014-07-29

申请号：US13361598

申请日：2012-01-30

申请人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

发明人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC分类号： H01L29/82

CPC分类号： H01L23/48 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

摘要翻译： 这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。 一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。 感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。 在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。