公开(公告)号：US08367467B2

公开(公告)日：2013-02-05

申请号：US12764805

申请日：2010-04-21

申请人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

发明人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC分类号： H01L21/60

CPC分类号： H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of making a semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件具有倒装芯片半导体管芯和衬底。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US20110260316A1

公开(公告)日：2011-10-27

申请号：US12764805

申请日：2010-04-21

申请人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

发明人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

摘要翻译： 半导体器件具有倒装芯片半导体管芯和衬底。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US20120146229A1

公开(公告)日：2012-06-14

申请号：US12965018

申请日：2010-12-10

申请人： SungWon Cho ,  JoHyun Bae ,  DaeSik Choi ,  DongSoo Moon

发明人： SungWon Cho ,  JoHyun Bae ,  DaeSik Choi ,  DongSoo Moon

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有封装基板底侧的封装基板，封装基板顶侧和封装基板窗口; 在封装基板上安装基极集成电路，基极集成电路具有基极非活性侧和面向封装基板顶侧的基极活性侧; 将下部内部连接器附接到基底主动侧和封装基板底侧，下部内部连接器通过封装基板窗口; 形成与基底集成电路和封装基板顶侧一致的上绝缘体，上绝缘体具有上绝缘顶侧; 并且通过所述上绝缘体形成周边绝缘连接器，所述外围绝缘连接器具有直接位于所述封装基板顶侧上的外围连接器底侧和与所述上绝缘顶侧共面的外围连接器顶侧。

公开(公告)号：US09324659B2

公开(公告)日：2016-04-26

申请号：US13195636

申请日：2011-08-01

申请人： SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

发明人： SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

IPC分类号： H01L21/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/05553 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die.

摘要翻译： 半导体器件具有安装到载体上的第一半导体晶片。 第二半导体晶片安装到第一半导体晶片。 单个第一和第二半导体晶片以分离堆叠的第一和第二半导体管芯。 层叠的半导体管芯之间的周边区域扩大。 在层叠的半导体管芯之间的载体上形成导电层。 或者，导电通孔部分地通过载体形成。 在第二半导体管芯上的接触焊盘和导电层或导电通孔之间形成接合线。 密封剂沉积在堆叠的半导体管芯，接合线和载体上。 去除载体以暴露第一半导体管芯上的导电层或导电通孔和接触焊盘。 直接在导电层和第一半导体管芯上的接触焊盘上形成凸起。

公开(公告)号：US20130069224A1

公开(公告)日：2013-03-21

申请号：US13235135

申请日：2011-09-16

申请人： Oh Han Kim ,  Ki Youn Jang ,  DaeSik Choi ,  DongSoo Moon

发明人： Oh Han Kim ,  Ki Youn Jang ,  DaeSik Choi ,  DongSoo Moon

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/82

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有列的可布线层; 安装与柱直接接触的集成电路结构; 以及形成伽马连接器以将该列电连接到集成电路结构。

公开(公告)号：US20130032952A1

公开(公告)日：2013-02-07

申请号：US13195636

申请日：2011-08-01

申请人： SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

发明人： SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/05553 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die.

摘要翻译： 半导体器件具有安装到载体上的第一半导体晶片。 第二半导体晶片安装到第一半导体晶片。 单个第一和第二半导体晶片以分离堆叠的第一和第二半导体管芯。 层叠的半导体管芯之间的周边区域扩大。 在层叠的半导体管芯之间的载体上形成导电层。 或者，导电通孔部分地通过载体形成。 在第二半导体管芯上的接触焊盘和导电层或导电通孔之间形成接合线。 密封剂沉积在堆叠的半导体管芯，接合线和载体上。 去除载体以暴露第一半导体管芯上的导电层或导电通孔和接触焊盘。 直接在导电层和第一半导体管芯上的接触焊盘上形成凸起。

公开(公告)号：US09093392B2

公开(公告)日：2015-07-28

申请号：US12965018

申请日：2010-12-10

申请人： SungWon Cho ,  JoHyun Bae ,  DaeSik Choi ,  DongSoo Moon

发明人： SungWon Cho ,  JoHyun Bae ,  DaeSik Choi ,  DongSoo Moon

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有封装基板底侧的封装基板，封装基板顶侧和封装基板窗口; 在封装基板上安装基极集成电路，基极集成电路具有基极非活性侧和面向封装基板顶侧的基极活性侧; 将下部内部连接器附接到基底主动侧和封装基板底侧，下部内部连接器通过封装基板窗口; 形成与基底集成电路和封装基板顶侧一致的上绝缘体，上绝缘体具有上绝缘顶侧; 并且通过所述上绝缘体形成周边绝缘连接器，所述外围绝缘连接器具有直接位于所述封装基板顶侧上的外围连接器底侧和与所述上绝缘顶侧共面的外围连接器顶侧。

公开(公告)号：US08513057B2

公开(公告)日：2013-08-20

申请号：US13235135

申请日：2011-09-16

申请人： Oh Han Kim ,  Ki Youn Jang ,  DaeSik Choi ,  DongSoo Moon

发明人： Oh Han Kim ,  Ki Youn Jang ,  DaeSik Choi ,  DongSoo Moon

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/82

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有列的可布线层; 安装与柱直接接触的集成电路结构; 以及形成伽马连接器以将该列电连接到集成电路结构。

公开(公告)号：US08193036B2

公开(公告)日：2012-06-05

申请号：US12882083

申请日：2010-09-14

申请人： SooMoon Park ,  ByoungWook Jang ,  DongSoo Moon

发明人： SooMoon Park ,  ByoungWook Jang ,  DongSoo Moon

IPC分类号： H01L21/00

CPC分类号： H01L21/54 ,  H01L21/563 ,  H01L24/743 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

摘要翻译： 半导体器件具有安装在衬底的表面上的半导体管芯。 模具底部填充分配针的宽度基本上等于半导体管芯的宽度。 分配针与半导体管芯的一侧流体连通。 将分注针的出口从半导体管芯的宽度均匀地沉积到半导体管芯和衬底之间的区域中，而不会发生分配针的移动。 分配针具有柄和T形构件的出口。 分配针可以在柄和出口之间具有多个极部。 分配针具有在柄和出口之间的板。 出口具有长度基本上等于或大于出口下边缘长度的上边缘。

公开(公告)号：US20110133325A1

公开(公告)日：2011-06-09

申请号：US12633789

申请日：2009-12-08

申请人： DongSoo Moon ,  Taewoo Lee ,  Soo-San Park ,  SooMoon Park ,  Sang-Ho Lee

发明人： DongSoo Moon ,  Taewoo Lee ,  Soo-San Park ,  SooMoon Park ,  Sang-Ho Lee

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供第一基板; 将部件安装在所述第一基板上; 将堆叠衬底安装在所述部件上，所述堆叠衬底具有内衬垫和连接到所述第一衬底的外衬垫; 将第一暴露的互连件安装在所述外垫上; 在所述堆叠衬底上形成第一封装，所述第一暴露的互连部分暴露，并且所述内衬垫部分地暴露在所述第一封装的凹部中; 以及将第二暴露的互连件安装在所述内垫上。