CONVERSION OF CRYPTOGRAPHIC KEY PROTECTION
    2.
    发明申请
    CONVERSION OF CRYPTOGRAPHIC KEY PROTECTION 有权
    转换关键保护

    公开(公告)号:US20110055560A1

    公开(公告)日:2011-03-03

    申请号:US12550667

    申请日:2009-08-31

    IPC分类号: G06F21/00 H04L9/00

    摘要: Protection of cryptographic keys is converted between one level of security and another level of security. The one level of security is different from the another level of security, and the another level of security includes the components of the one level of security.

    摘要翻译: 加密密钥的保护在一个安全级别和另一个安全级别之间进行转换。 一个级别的安全性与另一个安全级别不同,另一个级别的安全性包括一级安全性的组件。

    Dequeue operation using mask vector to manage input/output interruptions
    3.
    发明授权
    Dequeue operation using mask vector to manage input/output interruptions 失效
    使用掩码向量的出队操作来管理输入/输出中断

    公开(公告)号:US08762615B2

    公开(公告)日:2014-06-24

    申请号:US13332427

    申请日:2011-12-21

    IPC分类号: G06F9/48

    CPC分类号: G06F13/24

    摘要: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.

    摘要翻译: 发出命令以重置一个或多个待处理的中断指示符并仲裁中断的所有权。 响应于接收到该命令的处理器,检查所选待处理的中断指示符。 如果未设置所选待处理的中断指示符,则会检查另一个未决中断指示符,而不是提供否定响应并重新发出命令。 以这种方式,一个出队命令可以取代多个出队命令,减少了离开和重新进入中断处理程序的开销。 对于没有待复位的待处理中断指示符的情况,保留一个否定的响应。

    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS
    6.
    发明申请
    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
    用于转储储存元件的系统,方法和计算机程序产品

    公开(公告)号:US20090217009A1

    公开(公告)日:2009-08-27

    申请号:US12036520

    申请日:2008-02-25

    IPC分类号: G06F9/318

    摘要: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

    摘要翻译: 一种用于计算机系统中的翻译的系统,方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器,用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件,并用于产生位移或偏移值。 该系统还包括地址发生器,用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

    DEQUEUE OPERATION USING MASK VECTOR TO MANAGE INPUT/OUTPUT INTERRUPTIONS
    7.
    发明申请
    DEQUEUE OPERATION USING MASK VECTOR TO MANAGE INPUT/OUTPUT INTERRUPTIONS 失效
    使用掩码向量来管理输入/输出中断的DEQUEUE操作

    公开(公告)号:US20130166803A1

    公开(公告)日:2013-06-27

    申请号:US13332427

    申请日:2011-12-21

    IPC分类号: G06F13/24

    CPC分类号: G06F13/24

    摘要: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.

    摘要翻译: 发出命令以重置一个或多个待处理的中断指示符并仲裁中断的所有权。 响应于接收到该命令的处理器,检查所选待处理的中断指示符。 如果未设置所选待处理的中断指示符,则会检查另一个未决中断指示符,而不是提供否定响应并重新发出命令。 以这种方式,一个出队命令可以取代多个出队命令,减少了离开和重新进入中断处理程序的开销。 对于没有待复位的待处理中断指示符的情况,保留一个否定的响应。

    System, method and computer program product for translating storage elements
    8.
    发明授权
    System, method and computer program product for translating storage elements 有权
    用于翻译存储元件的系统,方法和计算机程序产品

    公开(公告)号:US07966474B2

    公开(公告)日:2011-06-21

    申请号:US12036520

    申请日:2008-02-25

    IPC分类号: G06F9/26

    摘要: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

    摘要翻译: 一种用于计算机系统中的翻译的系统,方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器,用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件,并用于产生位移或偏移值。 该系统还包括地址发生器,用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

    Apparatus and method for operating a symmetric cipher engine in cipher-block chaining mode
    10.
    发明申请
    Apparatus and method for operating a symmetric cipher engine in cipher-block chaining mode 失效
    用于在密码块链接模式下操作对称密码引擎的装置和方法

    公开(公告)号:US20090110189A1

    公开(公告)日:2009-04-30

    申请号:US12257439

    申请日:2008-10-24

    IPC分类号: H04L9/06

    CPC分类号: H04L9/0637 H04L2209/12

    摘要: An apparatus is disclosed for operating a symmetric cipher engine (SCE) in cipher-block chaining (CBC) mode, the apparatus comprises a crypto operation hardware comprising said SCE, an XOR stage, an apparatus for storing a chaining value comprising a state register of said SCE, an input latch supplying said crypto operation hardware with data, and an output latch. The data may be reordered for decipher operations. Furthermore, a method is disclosed for operating a SCE in CBC mode, wherein the method involves a crypto operation hardware that comprises said SCE and an XOR stage supplied with data. The method may also comprise using a state register of said SCE to apply a chaining value. Said method may comprise reordering data supplied to said crypto operation hardware for decipher operations.

    摘要翻译: 公开了一种用于在密码块链接(CBC)模式下操作对称密码引擎(SCE)的装置,该装置包括包含所述SCE的加密操作硬件,XOR级,用于存储链接值的装置,包括状态寄存器 所述SCE,向所述加密操作硬件提供数据的输入锁存器和输出锁存器。 数据可以被重新排序用于解密操作。 此外,公开了一种用于以CBC模式操作SCE的方法,其中所述方法涉及包括所述SCE和提供有数据的XOR级的密码操作硬件。 该方法还可以包括使用所述SCE的状态寄存器来应用链接值。 所述方法可以包括将提供给所述密码操作硬件的数据重新排序以进行解密操作。