公开(公告)号：US4763182A

公开(公告)日：1988-08-09

申请号：US941216

申请日：1986-12-12

申请人： Hiroji Ozaki ,  Shinichi Sato ,  Akira Tokui ,  Akira Kawai ,  Masayuki Nakajima ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Shinichi Sato ,  Akira Tokui ,  Akira Kawai ,  Masayuki Nakajima ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L27/10844 ,  H01L21/74 ,  H01L27/10805 ,  H01L29/0847 ,  H01L29/1083

摘要： A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.

摘要翻译： 半导体存储器件包括形成有电荷存储区域（5）的第一导电型半导体衬底（1）和用作位线的第二导电类型区域（6），以及第一导电型高浓度区域（8,11 形成浓度高于半导体衬底（1）的至少一位数，以分别包围电荷存储区域（5）和位线区域（6）。 因此，可以在高度集中区域（8）和电荷存储区域（5）之间以及高度集中区域（11）和位线区域（6）之间的界面中限定抵抗电子的势垒，从而防止故障 通过放射线如α射线的发生。

公开(公告)号：US4702796A

公开(公告)日：1987-10-27

申请号：US931583

申请日：1986-11-14

申请人： Masayuki Nakajima ,  Shinichi Sato ,  Akira Tokui ,  Akira Kawai ,  Masao Nagatomo ,  Hiroji Ozaki

发明人： Masayuki Nakajima ,  Shinichi Sato ,  Akira Tokui ,  Akira Kawai ,  Masao Nagatomo ,  Hiroji Ozaki

IPC分类号： H01L21/74 ,  H01L21/8242 ,  H01L23/556 ,  H01L21/04 ,  B44C1/22 ,  H01L21/22 ,  H01L21/306

CPC分类号： H01L27/10844 ,  H01L21/74 ,  H01L23/556 ,  H01L2224/16245 ,  H01L2224/48247 ,  Y10S438/965

摘要： The present invention is a method for fabricating a semiconductor device, wherein impurity is selectively diffused to surround a region (7) of a second conductivity type as a bit line formed on a semiconductor substrate (1), thereby forming an impurity diffused region (9) of a first conductivity type having high density and, by extending the impurity diffused region (9) in the element separating step to form a high density region of the first conductivity type having high density.

摘要翻译： 本发明是一种制造半导体器件的方法，其中杂质被选择性扩散以包围形成在半导体衬底（1）上的位线的第二导电类型的区域（7），从而形成杂质扩散区域（9 ），并且通过在元件分离步骤中扩展杂质扩散区域（9）以形成具有高密度的第一导电类型的高密度区域。

公开(公告)号：US4956310A

公开(公告)日：1990-09-11

申请号：US195672

申请日：1988-10-05

申请人： Akira Tokui ,  Shinichi Sato ,  Akira Kawai ,  Masayuki Nakajima ,  Hiroji Ozaki ,  Masao Nagatomo

发明人： Akira Tokui ,  Shinichi Sato ,  Akira Kawai ,  Masayuki Nakajima ,  Hiroji Ozaki ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/10844 ,  H01L21/74 ,  H01L27/10805 ,  H01L29/0847 ,  H01L29/1083

摘要： A semiconductor memory device in accordance with the present invention comprises: a semiconductor substrate (1) of a first conductivity type; a charge storage region (6) and a bit line region (7) of a second conductivity type formed on a main surface of the substrate; highly doped regions (12a, 12b) of the first conductivity type formed respectively contiguous to only the bottom boundaries of the charge storage region (6) and the bit line region (7).

摘要翻译： 根据本发明的半导体存储器件包括：第一导电类型的半导体衬底（1）; 形成在基板的主表面上的第二导电类型的电荷存储区域（6）和位线区域（7） 第一导电类型的高掺杂区域（12a，12b）分别形成为仅与电荷存储区域（6）和位线区域（7）的底部边界邻接。

公开(公告)号：US4984055A

公开(公告)日：1991-01-08

申请号：US267103

申请日：1988-11-07

申请人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

发明人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/485 ,  H01L23/522 ,  H01L2924/0002

摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.

摘要翻译： 公开了具有多个导电层的半导体器件。 该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。 半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。 由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9） 。 形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。 在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。 三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面 绝缘层。

公开(公告)号：US4956692A

公开(公告)日：1990-09-11

申请号：US266704

申请日：1988-11-03

申请人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  H01L21/31 ,  H01L21/334 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/76205 ,  H01L27/10829

摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

摘要翻译： 在半导体衬底的主表面上以预定距离形成两个沟槽。 在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。 在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。 通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。 然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

公开(公告)号：US5323343A

公开(公告)日：1994-06-21

申请号：US77971

申请日：1993-06-18

申请人： Ikuo Ogoh ,  Masao Nagatomo

发明人： Ikuo Ogoh ,  Masao Nagatomo

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105

摘要： A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

摘要翻译： 根据本发明的DRAM包括具有由一个传输栅极晶体管（10）和电容器（11）构成的存储单元的存储单元阵列和具有LDD结构的MOS晶体管（45a）的外围电路。 至少连接到传输门晶体管的电容器的源极/漏极区域（19）由低浓度杂质区域（19a）形成。 低浓度杂质区域的杂质浓度基本上等于外围电路的LDD MOS晶体管的低浓度源极/漏极区域（31）的杂质浓度。 传输栅极晶体管的低浓度/漏极区域是通过在高浓度离子注入步骤时对其外围电路的MOS晶体管的高浓度源极/漏极形成的表面进行掩蔽来形成的。 通过省略高浓度离子注入步骤，消除了传输栅晶体管的源极/漏极区的衬底缺陷，以抑制电荷从电容器的泄漏。

公开(公告)号：US5164806A

公开(公告)日：1992-11-17

申请号：US698690

申请日：1991-05-13

申请人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

发明人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/765

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/765 ,  H01L29/6656 ,  Y10S257/90

摘要： An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film.A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region.An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.

摘要翻译： 用于隔离半导体衬底的元件的元件隔离结构具有在有源区中形成的MOS晶体管的源极/漏极之间具有低于源极/漏极和沟道截止区域的浓度的杂质区域和 在LOCOS膜下形成的通道停止区域。 场屏蔽隔离结构在有源区中形成的MOS晶体管的源极/漏极与由场屏蔽电极层覆盖的衬底表面区域之间具有低浓度杂质区域。 低浓度杂质区域改善了与元件隔离区域的边界区域的结击穿电压。 通过倾斜旋转离子注入方法将改进的LOCOS膜形成在衬底的表面上的非晶区域中，通过热氧化形成非晶区域。 该方法抑制鸟喙的出现。

公开(公告)号：US5047359A

公开(公告)日：1991-09-10

申请号：US342673

申请日：1989-04-26

申请人： Masao Nagatomo

发明人： Masao Nagatomo

IPC分类号： H01L21/76 ,  H01L21/265

CPC分类号： H01L21/26586

摘要： The present invention relates to a method of manufacturing a semiconductor device. In order to controllably introduce impurities into the side wall of a trench 2a by ion implantation impurity ions are directed at a predetermined angle into the side wall of the trench 2a provided in a wafer 2a and, for implantation thereof, at the same time, the wafer 2 is rotated around an ion implantation axis at a rotational speed related to the ion implantation current.

摘要翻译： 本发明涉及半导体器件的制造方法。 为了通过离子注入将杂质可控地引入沟槽2a的侧壁中，杂质离子以预定角度被引导到设置在晶片2a中的沟槽2a的侧壁中，并且为了植入它们，同时， 晶片2以与离子注入电流相关的旋转速度绕离子注入轴旋转。

公开(公告)号：US4333226A

公开(公告)日：1982-06-08

申请号：US209889

申请日：1980-11-24

申请人： Haruhiko Abe ,  Masao Nagatomo ,  Natsuro Tsubouchi ,  Hiroshi Harada ,  Junichi Mitsuhashi

发明人： Haruhiko Abe ,  Masao Nagatomo ,  Natsuro Tsubouchi ,  Hiroshi Harada ,  Junichi Mitsuhashi

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L21/316 ,  H01L21/321 ,  H01L21/768 ,  B05D3/06 ,  B05D5/12 ,  H01L21/312

CPC分类号： H01L21/76888 ,  H01L21/31683 ,  H01L21/321 ,  Y10S148/02 ,  Y10S148/117 ,  Y10S438/911

摘要： A thin film of a metal which is capable of oxidation and sublimation is formed on a major surface of a semiconductor substrate, and a portion of a major surface of the thin metallic film is irradiated with an oxygen ion beam to convert a portion of the thin metallic film to an oxide, and subsequently the thin metallic film is heat treated to remove the oxide by sublimation, whereby electrodes or wiring for a semiconductor integrated circuit are formed by the remaining thin metallic film.

摘要翻译： 在半导体衬底的主表面上形成能够氧化和升华的金属薄膜，并且用氧离子束照射薄金属膜的主表面的一部分，以将薄的一部分 金属膜与氧化物接触，随后通过升华来对金属薄膜进行热处理以除去氧化物，由剩余的薄金属膜形成用于半导体集成电路的电极或布线。

公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。