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    Structure of stacked vias in multiple layer electronic device carriers
    1.
    发明申请
    Structure of stacked vias in multiple layer electronic device carriers 有权
    多层电子设备载体中堆叠通孔的结构

    公开(公告)号：US20050156319A1

    公开(公告)日：2005-07-21

    申请号：US10515511

    申请日：2003-04-18

    申请人： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

    发明人： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

    IPC分类号： H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

    CPC分类号： H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/0979 ,  H01L2924/00

    摘要： A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis. In a preferred embodiment, the shape of these aligned conductive tracks looks like a disk or an annular ring and four vias are used to connect two adjacent conductive layers. These four vias are symmetrically disposed on each of said conductive track. The position of the vias between a first and a second adjacent conductive layers and between a second and a third adjacent conductive layers forms an angle of 45° according to z axis.

    摘要翻译： 公开了一种适于通过电子设备载体的导电层传输高频信号或高强度电流的堆叠通孔结构（200）。 叠置的通孔结构包括属于由电介质层（120）分开的根据z轴对准的三个相邻导电层（110a，110b，110c）的至少三个导电轨道（205a，205b，205c）。 这些导电轨道之间的连接通过在每个导电层之间的至少两个通孔（210,215）进行。 连接到导电轨道的一侧的通孔布置成使得它们不与根据z轴连接到另一侧的那些对准。 在优选实施例中，这些对准的导电轨迹的形状看起来像盘或环形环，并且四个通孔用于连接两个相邻的导电层。 这四个通孔对称地设置在每个导电轨道上。 在第一和第二相邻导电层之间以及第二和第三相邻导电层之间的通孔的位置根据z轴形成45°的角度。

    OPTIMIZED PLATING PROCESS FOR MULTILAYER PRINTED CIRCUIT BOARDS HAVING EDGE CONNECTORS
    10.
    发明申请
    OPTIMIZED PLATING PROCESS FOR MULTILAYER PRINTED CIRCUIT BOARDS HAVING EDGE CONNECTORS 审中-公开
    具有边缘连接器的多层印刷电路板优化镀层工艺

    公开(公告)号：US20060008970A1

    公开(公告)日：2006-01-12

    申请号：US11160780

    申请日：2005-07-08

    申请人： Stefano Oggioni ,  Giorgio Viero

    发明人： Stefano Oggioni ,  Giorgio Viero

    IPC分类号： H01L21/8238

    CPC分类号： H05K3/244 ,  H05K1/117 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2203/054 ,  H05K2203/058 ,  H05K2203/072 ,  H05K2203/0723

    摘要： A process for manufacturing printed wire boards with hard plated sliding contact tabs and soft plated wire bond pads. Sliding contact tabs are covered by a protective coating after being hard plated thus allowing the soft plating of wire bond pads without damaging the hard plated sliding contact tabs. In a preferred embodiment, the hard plating includes the step of electroplating nickel on the sliding contact tabs, followed by electroplating an alloy of gold and cobalt, using standard electroplating process. An electro-less soft plating process includes the steps of plating a nickel layer on the wire bond pads and then a gold layer after having “flash-etched” the copper seeding.

    摘要翻译： 一种制造具有硬镀滑动接触片和软电镀线接合垫的印刷线路板的方法。 硬接触后，滑动接触片被保护层覆盖，从而允许电焊接焊盘的软电镀，而不会损坏硬镀滑动接触片。 在优选实施例中，硬镀层包括在滑动接触片上电镀镍的步骤，然后使用标准电镀工艺电镀金和钴的合金。 无电镀软工艺包括以下步骤：在铜接合焊盘上镀镍层，然后在“闪光蚀刻”铜接种之后镀金层。