公开(公告)号：US08669658B2

公开(公告)日：2014-03-11

申请号：US11782384

申请日：2007-07-24

申请人： Mon-Chin Tsai ,  Hsiu-Mei Yo ,  Chien-Min Lin ,  Chia-Jen Cheng ,  Li-Hsin Tseng

发明人： Mon-Chin Tsai ,  Hsiu-Mei Yo ,  Chien-Min Lin ,  Chia-Jen Cheng ,  Li-Hsin Tseng

IPC分类号： H01L23/48

CPC分类号： H01L23/66 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01014 ,  H01L2924/00

摘要： A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.

摘要翻译： 提供了用于高频应用的用于制造无串扰晶片级芯片级封装（WLCSP）结构的结构，系统和方法。 示例性实施例包括其上各种层和结构形成电路的衬底，形成在衬底上并与电路耦合的信号引脚，环绕信号引脚的接地环和耦合到接地环的接地焊料凸块。

公开(公告)号：US20090026608A1

公开(公告)日：2009-01-29

申请号：US11782384

申请日：2007-07-24

申请人： Mon-Chin Tsai ,  Hsiu-Mei Yo ,  Chien-Min Lin ,  Chia-Jen Cheng ,  Li-Hsin Tseng

发明人： Mon-Chin Tsai ,  Hsiu-Mei Yo ,  Chien-Min Lin ,  Chia-Jen Cheng ,  Li-Hsin Tseng

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/66 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01014 ,  H01L2924/00

摘要： A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.

摘要翻译： 提供了用于高频应用的用于制造无串扰晶片级芯片级封装（WLCSP）结构的结构，系统和方法。 示例性实施例包括其上各种层和结构形成电路的衬底，形成在衬底上并与电路耦合的信号引脚，环绕信号引脚的接地环和耦合到接地环的接地焊料凸块。

公开(公告)号：US07391118B2

公开(公告)日：2008-06-24

申请号：US10923669

申请日：2004-08-24

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

摘要翻译： 提供了一种通过倒装芯片连接的嵌入式无源部件的集成电路器件，其包括倒装芯片和虚设芯片。 虚拟芯片至少包括嵌入式无源元件，多个再分配迹线和多个倒装芯片焊盘。 倒装芯片比虚拟芯片小，并且用倒装芯片焊盘安装在虚设芯片的表面上。 嵌入式无源元件经由再分配迹线和倒装芯片焊盘与倒装芯片电连接。 在虚拟芯片的表面的周边区域配置有多个焊锡球。

公开(公告)号：US20080233676A1

公开(公告)日：2008-09-25

申请号：US12153584

申请日：2008-05-21

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L21/00

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

摘要翻译： 提供了一种通过倒装芯片连接的嵌入式无源部件的集成电路器件，其包括倒装芯片和虚设芯片。 虚拟芯片至少包括嵌入式无源元件，多个再分配迹线和多个倒装芯片焊盘。 倒装芯片比虚拟芯片小，并且用倒装芯片焊盘安装在虚设芯片的表面上。 嵌入式无源元件经由再分配迹线和倒装芯片焊盘与倒装芯片电连接。 在虚拟芯片的表面的周边区域配置有多个焊锡球。

公开(公告)号：US20050181538A1

公开(公告)日：2005-08-18

申请号：US10876581

申请日：2004-06-28

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00014

摘要： A manufacturing method of a semiconductor device for a wire-bonding and flip-chip bonding package mainly comprises the following steps. First, a chip having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, an under bump metallurgy layer having an aluminum layer, a nickel-vanadium layer and a copper layer is formed on each of the bonding pads. Then, a portion of the copper layer and the nickel-vanadium layer formed over some of the bonding pads is removed so as to leave a portion of the copper layer and the nickel-vanadium layer remained over some of the bonding pads to form patterned copper layers and patterned nickel-vanadium layers. Next, a plurality of solder bumps are formed on the patterned copper layers. Finally, a reflowing process is performed to have the solder bumps secured to the patterned copper layers. In addition, a semiconductor device formed by the manufacturing method is provided.

摘要翻译： 用于引线接合和倒装芯片接合封装的半导体器件的制造方法主要包括以下步骤。 首先，提供具有多个接合焊盘的芯片和暴露接合焊盘的钝化层。 接下来，在每个接合焊盘上形成具有铝层，镍钒层和铜层的凸块下金属层。 然后，去除在一些焊盘上形成的铜层和镍 - 钒层的一部分，以便留下铜层的一部分并且镍 - 钒层保留在一些焊盘上以形成图案化铜 层和图案化的镍钒层。 接下来，在图案化的铜层上形成多个焊料凸块。 最后，进行回流处理以使焊料凸起固定到图案化的铜层。 此外，提供通过该制造方法形成的半导体器件。

公开(公告)号：US20050046041A1

公开(公告)日：2005-03-03

申请号：US10923669

申请日：2004-08-24

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L25/065 ,  H01L25/16 ,  H01L27/10

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

摘要翻译： 提供了一种通过倒装芯片连接的嵌入式无源部件的集成电路器件，其包括倒装芯片和虚设芯片。 虚拟芯片至少包括嵌入式无源元件，多个再分配迹线和多个倒装芯片焊盘。 倒装芯片比虚拟芯片小，并且用倒装芯片焊盘安装在虚设芯片的表面上。 嵌入式无源元件经由再分配迹线和倒装芯片焊盘与倒装芯片电连接。 在虚拟芯片的表面的周边区域配置有多个焊锡球。

公开(公告)号：US20090166873A1

公开(公告)日：2009-07-02

申请号：US11965157

申请日：2007-12-27

申请人： Wen-Kun Yang ,  Jui-Hsien Chang ,  Chi-Chen Lee ,  Mon-Chin Tsai

发明人： Wen-Kun Yang ,  Jui-Hsien Chang ,  Chi-Chen Lee ,  Mon-Chin Tsai

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L27/14618 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3512 ,  H01L2924/00

摘要： The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die.

摘要翻译： 半导体管芯的互连结构包括：在有源表面上具有接合焊盘的管芯; 通过粘合材料将芯片的侧壁（边缘）附着在芯上; 通过粘合胶粘在模具的活性表面上的隔离基体; 从芯片的背面开口的通硅通孔（TSV）露出接合焊盘; 通过硅通孔将接合焊盘耦合到端子金属焊盘的堆积层; 焊球在端子焊盘上熔化，其中位于芯和/或模具上的端子焊盘。

公开(公告)号：US20050059235A1

公开(公告)日：2005-03-17

申请号：US10918434

申请日：2004-08-16

申请人： Been-Jon Woo ,  Mon-Chin Tsai

发明人： Been-Jon Woo ,  Mon-Chin Tsai

IPC分类号： H01L21/304 ,  H01L21/306 ,  H01L21/316 ,  H01L21/321 ,  H01L21/4763 ,  H01L21/8242 ,  H01S3/08

CPC分类号： H01L21/32105 ,  H01L21/3212

摘要： A method for improving the flatness of an oxide layer comprising the steps of providing a semiconductor structure, forming a polysilicon layer on the semiconductor structure, utilizing chemical mechanical polishing to planarize the polysilicon layer, and forming an oxide layer on the polysilicon layer. As a result of using chemical mechanical polishing on the polysilicon layer, an improved flatness of the subsequently formed oxide layer is achieved.

摘要翻译： 一种用于提高氧化物层的平坦度的方法，包括以下步骤：提供半导体结构，在半导体结构上形成多晶硅层，利用化学机械抛光来平坦化多晶硅层，以及在多晶硅层上形成氧化物层。 作为在多晶硅层上使用化学机械抛光的结果，实现随后形成的氧化物层的改善的平坦度。

公开(公告)号：US07670876B2

公开(公告)日：2010-03-02

申请号：US12153584

申请日：2008-05-21

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

摘要翻译： 提供了一种通过倒装芯片连接的嵌入式无源部件的集成电路器件，其包括倒装芯片和虚设芯片。 虚拟芯片至少包括嵌入式无源元件，多个再分配迹线和多个倒装芯片焊盘。 倒装芯片比虚拟芯片小，并且用倒装芯片焊盘安装在虚设芯片的表面上。 嵌入式无源元件经由再分配迹线和倒装芯片焊盘与倒装芯片电连接。 在虚拟芯片的表面的周边区域配置有多个焊锡球。

公开(公告)号：US20060197191A1

公开(公告)日：2006-09-07

申请号：US11164970

申请日：2005-12-13

申请人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

发明人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

IPC分类号： H01L23/58

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

摘要： A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.

摘要翻译： 提供了包括基板，电路单元，多个接合焊盘，第一钝化层和再分配层的芯片结构。 电路单元设置在基板上，并且接合焊盘设置在电路单元上。 此外，第一钝化层设置在电路单元上并且暴露接合焊盘。 Ti / Cu / Ti多层结构的再分布层设置在第一钝化层上，并与接合焊盘电连接。 此外，Ti / Cu / Ti多层结构的再分布层具有优异的导电性，使得芯片结构的电特性得到有效的提高。