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18 条记录 (耗时 0.028 秒)

    Channel estimation and synchronization with preamble using polyphase code
    4.
    发明授权
    Channel estimation and synchronization with preamble using polyphase code 失效
    使用多相码的信道估计和前同步码同步

    公开(公告)号：US07453794B2

    公开(公告)日：2008-11-18

    申请号：US10737339

    申请日：2003-12-16

    申请人： Yuguang Fang ,  Byung-Seo Kim

    发明人： Yuguang Fang ,  Byung-Seo Kim

    IPC分类号： H04J11/00

    CPC分类号： H04L27/2656 ,  H04L5/0007 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0226 ,  H04L27/2605 ,  H04L27/2613 ,  H04L27/2662

    摘要： A preamble for an OFDM signal synchronizes (104) and estimates (106) the sub-channels with only one code. One polyphase code sequence is used repeatedly for the preamble. The preamble is spread out over the bandwidth, which is the same as an OFDM symbol in the frequency domain and has good autocorrelation characteristics in the time domain. All OFDM signals are added with this preamble at the beginning of the OFDM signal and transmitted on the channel at a transmitter (50). At the receiving end, the receiver (100) first does the autocorrelation process to find out a peak value for synchronization in the time domain. Then, since the polyphase code is known at the receiver, the signal to noise ratio for each sub-carrier is calculated in the frequency domain and smoothed using the normal (Gaussian) distribution to provide the channel estimation. Since the synchronization and channel estimation are processed with a single preamble, the overhead for these two functions is significantly reduced.

    摘要翻译： OFDM信号的前导码同步（104）并仅使用一个码估计（106）子信道。 对于前同步码重复使用一个多相码序列。 前导码在带宽上扩展，与频域中的OFDM符号相同，并且在时域中具有良好的自相关特性。 所有OFDM信号在OFDM信号的开始处与该前同步码相加，并在发射机（50）的信道上发送。 在接收端，接收机（100）首先进行自相关处理，以找出在时域中同步的峰值。 然后，由于在接收机处已知多相码，所以在频域中计算每个子载波的信噪比并使用正态（高斯）分布进行平滑，以提供信道估计。 由于使用单个前同步码来处理同步和信道估计，所以这两个功能的开销显着降低。

    Multi-layer differential phase shift keying with bit-interleaved coded modulation and OFDM
    5.
    发明申请
    Multi-layer differential phase shift keying with bit-interleaved coded modulation and OFDM 失效
    具有位交织编码调制和OFDM的多层差分相移键控

    公开(公告)号：US20050111590A1

    公开(公告)日：2005-05-26

    申请号：US10721533

    申请日：2003-11-25

    申请人： Yuguang Fang ,  Byung-Seo Kim

    发明人： Yuguang Fang ,  Byung-Seo Kim

    IPC分类号： H04L27/20 ,  H04L27/22

    CPC分类号： H04L27/205 ,  H04L27/2071 ,  H04L27/2075

    摘要： An efficient system and method for modulation and demodulation to achieve a high data rate using Bit-Interleaved Coded Modulation and OFDM uses either a coherent or a non-coherent transmission scheme using differential modulation. In order to maintain a high data rate impervious to sudden phase changes, a communication system uses an efficient constellation having multiple rings with different sizes and modulation/demodulation schemes utilizing this constellation. In power line communications, the channel gain information is obtained easily at a receiver (100) while the phase information is not. Thus, the communication system uses an absolute magnitude and differential phase coding for modulation and demodulation of the signals.

    摘要翻译： 用于使用比特交错编码调制实现高数据速率的调制和解调的有效系统和方法使用差分调制使用相干或非相干传输方案。 为了保持突发相位变化的高数据速率，通信系统使用具有不同大小的多个环的有效星座和利用该星座的调制/解调方案。 在电力线通信中，在相位信息不是在接收器（100）处容易地获得信道增益信息。 因此，通信系统使用绝对幅度和差分相位编码来进行信号的调制和解调。

    Semiconductor memory device having resistor and method of fabricating the same
    6.
    发明申请
    Semiconductor memory device having resistor and method of fabricating the same 有权
    具有电阻器的半导体存储器件及其制造方法

    公开(公告)号：US20050009261A1

    公开(公告)日：2005-01-13

    申请号：US10911157

    申请日：2004-08-02

    申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

    发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

    IPC分类号： H01L21/108 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L21/8238

    CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

    摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

    摘要翻译： 提供一种在周边区域具有电阻器的半导体器件及其制造方法。 在半导体基板上形成模层。 图案化模具层以在模具层中形成第一模制孔和第二模制孔。 存储节点层形成在模具层以及第一和第二模制孔中。 存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

    Phase change memory and method of fabricating the same
    7.
    发明申请
    Phase change memory and method of fabricating the same 失效
    相变记忆及其制造方法

    公开(公告)号：US20090163023A1

    公开(公告)日：2009-06-25

    申请号：US12314884

    申请日：2008-12-18

    申请人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    发明人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

    摘要翻译： 制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度 大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面 硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

    Semiconductor memory device having resistor and method of fabricating the same
    8.
    发明授权
    Semiconductor memory device having resistor and method of fabricating the same 有权
    具有电阻器的半导体存储器件及其制造方法

    公开(公告)号：US07319254B2

    公开(公告)日：2008-01-15

    申请号：US10911157

    申请日：2004-08-02

    申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

    发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/0392

    CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

    摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

    摘要翻译： 提供一种在周边区域具有电阻器的半导体器件及其制造方法。 在半导体基板上形成模层。 图案化模具层以在模具层中形成第一模制孔和第二模制孔。 存储节点层形成在模具层以及第一和第二模制孔中。 存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

    Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell
    9.
    发明申请
    Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
    具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法

    公开(公告)号：US20060120148A1

    公开(公告)日：2006-06-08

    申请号：US11238381

    申请日：2005-09-29

    申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

    发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

    IPC分类号： G11C11/00

    CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

    摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

    摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

    Method of fabricating a semiconductor memory device having resistor
    10.
    发明授权
    Method of fabricating a semiconductor memory device having resistor 有权
    制造具有电阻器的半导体存储器件的方法

    公开(公告)号：US06794247B2

    公开(公告)日：2004-09-21

    申请号：US10272670

    申请日：2002-10-16

    申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

    发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

    IPC分类号： H01L21336

    CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

    摘要： A method of fabricating a semiconductor device having a cell array area and a peripheral circuit area is provided. A mold layer is formed on a substrate in the cell array area and the peripheral circuit area. A plurality of first molding holes are formed in the mold layer in the cell array area. A second molding hole is formed in the mold layer in the peripheral circuit area. A storage node layer is formed on the mold layer, in the first molding holes and in the second molding hole. A plurality of storage nodes are formed in the first molding holes and a first portion of a resistor is formed in the second molding hole by removing a portion of the storage node layer. The first portion of the resistor is formed of the storage node layer.

    摘要翻译： 提供一种制造具有单元阵列区域和外围电路区域的半导体器件的方法。 在单元阵列区域和外围电路区域的基板上形成模层。 多个第一成型孔形成在电池阵列区域的模具层中。 在外围电路区域的模具层中形成第二模制孔。 存储节点层形成在模具层上，第一模制孔和第二模制孔中。 多个存储节点形成在第一模制孔中，并且通过去除存储节点层的一部分，在第二模制孔中形成电阻器的第一部分。 电阻器的第一部分由存储节点层形成。