公开(公告)号：US4367492A

公开(公告)日：1983-01-04

申请号：US212434

申请日：1980-12-03

申请人： Nozomu Harada ,  Akihiko Furukawa ,  Yukio Endo ,  Okio Yoshida

发明人： Nozomu Harada ,  Akihiko Furukawa ,  Yukio Endo ,  Okio Yoshida

IPC分类号： H01L27/148 ,  H04N5/335 ,  H04N5/369 ,  H04N5/3728 ,  H04N9/04 ,  H04N9/07 ,  H04N3/14

CPC分类号： H04N9/045 ,  H01L27/14825 ,  H01L27/14831 ,  H01L27/14868 ,  H04N3/155 ,  H04N3/1556

摘要： A plurality of photosensitive sections, each having two photosensitive rows, and a plurality of readout sections, each having two readout rows, are alternately distributed in the horizontal direction. The picture element signals of the photosensitive rows each adjacent to each of two readout rows are synthesized for each line. Pseudo-picture element signals are synthesized from the synthesized picture element signals, and the pseudo-picture element signals are used as the picture element signals corresponding to the readout sections.

摘要翻译： 具有两个感光行的多个感光部分和具有两个读出行的多个读出部分在水平方向上交替分布。 每行相邻的感光行的像素信号被合成为每行。 从合成的像素信号合成伪像素信号，将伪像素信号用作对应于读出部分的像素信号。

公开(公告)号：US09536942B2

公开(公告)日：2017-01-03

申请号：US14363914

申请日：2012-08-02

申请人： Tsuyoshi Kawakami ,  Kenji Hamada ,  Kohei Ebihara ,  Akihiko Furukawa ,  Yuji Murakami

发明人： Tsuyoshi Kawakami ,  Kenji Hamada ,  Kohei Ebihara ,  Akihiko Furukawa ,  Yuji Murakami

IPC分类号： H01L21/266 ,  H01L29/78 ,  H01L29/872 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423

CPC分类号： H01L29/063 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层的上层部分中的有源区和从有源区的边缘朝向外部设置以围绕有源区的多个电场弛豫层。 多个电场弛豫层包括彼此相邻交替设置的多个第一电场弛豫层和多个第二电场弛豫层，第一电场弛豫层和彼此相邻的第二电场弛豫层形成 一套。 第二导电类型的杂质以第一表面密度注入第一电场弛豫层，其宽度随着活性区域的变小而变小。 第二导电类型的杂质以比第一表面密度低的第二表面密度注入第二电场弛豫层，其宽度随着活性区域的变大而变大。

公开(公告)号：US08716717B2

公开(公告)日：2014-05-06

申请号：US13816511

申请日：2011-04-15

申请人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Naruhisa Miura ,  Yasuhiro Kagawa ,  Kenji Hamada ,  Yoshiyuki Nakaki

发明人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Naruhisa Miura ,  Yasuhiro Kagawa ,  Kenji Hamada ,  Yoshiyuki Nakaki

IPC分类号： H01L29/12

CPC分类号： H01L29/12 ,  H01L21/0465 ,  H01L21/265 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611 ,  H01L29/872

摘要： A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.

摘要翻译： 在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层，第二RESURF层，第三RESURF层，第四RESURF层和第五RESURF层。 第二RESURF层配置有具有等于第一RESURF层的注入量的小区域，并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。 第四RESURF层配置有具有等于第三RESURF层的注入量的小区域，并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。

公开(公告)号：US20140001472A1

公开(公告)日：2014-01-02

申请号：US13995993

申请日：2011-05-18

申请人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi

发明人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi

IPC分类号： H01L29/16 ,  H01L21/02

CPC分类号： H01L21/02529 ,  H01L21/8213 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/872

摘要： A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.

摘要翻译： 一种碳化硅半导体器件，包括测量碳化硅半导体元件的温度的SBD。 碳化硅半导体器件包括形成在碳化硅外延衬底上的MOSFET和测量MOSFET的温度的SBD部分。 SBD部分包括在碳化硅漂移层的表面部分中的n型阴极区域; 在阴极区域形成的阳极钛电极，用作肖特基电极的电极; 形成在碳化硅漂移层的表面部分中以与阴极区接触的n型阴极接触区域，其浓度高于阴极区域; 形成在阴极接触区域上的阴极欧姆电极; 以及形成在碳化硅漂移层内以围绕阴极区域和阴极接触区域的周边的第一p型阱区域。

公开(公告)号：US06228697B1

公开(公告)日：2001-05-08

申请号：US09158602

申请日：1998-09-23

申请人： Akihiko Furukawa ,  Yoshikazu Yoneda

发明人： Akihiko Furukawa ,  Yoshikazu Yoneda

IPC分类号： H01L218238

CPC分类号： H01L27/11526 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： A method of manufacturing a semiconductor device is provided in which a semiconductor device including a plurality of FETs having different threshold voltages and gate insulating films with different film thicknesses can be manufactured in a simplified process. Specifically, a first gate insulating film is formed on the main surface of a semiconductor substrate. On the first gate insulating film, a first protection film is formed. In regions A and B in each of which an FET having a second gate insulating film with a film thickness different from that of the first gate insulating film is to be formed, the first gate insulating film and the first protection film are removed to expose the surface of the semiconductor substrate. At the same time, the first protection film is left in regions other than the regions A and B. Using the first protection film as a mask, an impurity is implanted into the semiconductor substrate in the regions A and B.

摘要翻译： 提供一种制造半导体器件的方法，其中可以以简化的工艺制造包括具有不同阈值电压的多个FET的半导体器件和具有不同膜厚度的栅极绝缘膜。 具体地，在半导体衬底的主表面上形成第一栅极绝缘膜。 在第一栅极绝缘膜上形成第一保护膜。 在每个区域A和B中，形成具有不同于第一栅极绝缘膜的膜厚度的第二栅极绝缘膜的FET，去除第一栅极绝缘膜和第一保护膜以暴露 半导体衬底的表面。 同时，将第一保护膜留在除区域A和B之外的区域中。使用第一保护膜作为掩模，在区域A和B中的半导体衬底中注入杂质。

公开(公告)号：US6144072A

公开(公告)日：2000-11-07

申请号：US231548

申请日：1999-01-15

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US5905286A

公开(公告)日：1999-05-18

申请号：US794504

申请日：1997-02-04

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

摘要翻译： 在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。 在该半导体器件中，半导体层的上侧部分是圆形的。 由此，可以防止半导体层的上侧部分的电场集中。 结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。 通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。 因此，不会在制造过程中引起缺点。

公开(公告)号：US09224860B2

公开(公告)日：2015-12-29

申请号：US13992574

申请日：2011-12-05

申请人： Yasuhiro Kagawa ,  Akihiko Furukawa ,  Shiro Hino ,  Hiroshi Watanabe ,  Masayuki Imaizumi

发明人： Yasuhiro Kagawa ,  Akihiko Furukawa ,  Shiro Hino ,  Hiroshi Watanabe ,  Masayuki Imaizumi

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/66348 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region.

摘要翻译： 一种沟槽栅型半导体器件，其可以防止在关断时在栅电极下方的沟槽部分流入保护扩散层的位移电流引起的栅极绝缘膜的破坏，并且同时通过 缩小细胞间距 半导体器件包括嵌入到穿透基极区域的沟槽中的栅电极。 栅电极在平面图中设置为格子状，并且在其下方的部分的漂移层中形成保护扩散层。 由栅电极分隔的至少一个块是其上完全形成沟槽的保护接触区域。 用于在沟槽的底部连接保护性扩散层和源电极的保护接点设置在保护接触区域上。

公开(公告)号：US20150108564A1

公开(公告)日：2015-04-23

申请号：US14400025

申请日：2013-03-12

申请人： Naruhisa Miura ,  Shiro Hino ,  Akihiko Furukawa ,  Yuji Abe ,  Shuhei Nakata ,  Masayuki Imaizumi ,  Yasuhiro Kagawa

发明人： Naruhisa Miura ,  Shiro Hino ,  Akihiko Furukawa ,  Yuji Abe ,  Shuhei Nakata ,  Masayuki Imaizumi ,  Yasuhiro Kagawa

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/8083

摘要： A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.

摘要翻译： MOSFET的源极区域包括：源极接触区域，连接到源极焊盘; 源极延伸区域，其邻近阱区域中的沟道区域; 以及源极电阻控制区域，其布置在源极延伸区域和源极接触区域之间。 源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。 这三个区域串联连接在源极区和阱区中的沟道区之间。

公开(公告)号：US09006819B2

公开(公告)日：2015-04-14

申请号：US13639738

申请日：2011-02-08

申请人： Shiro Hino ,  Naruhisa Miura ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Masayuki Imaizumi

发明人： Shiro Hino ,  Naruhisa Miura ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Masayuki Imaizumi

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的第一主表面上的第一导电类型的漂移层，形成为围绕电池的第二导电类型的第二阱区域 漂移层的区域和用于通过设置成穿过第二阱区域上的栅极绝缘膜设置的第一阱接触孔电连接第二阱区域和电池区域的源极区域的源极焊盘，提供第二阱接触孔 以穿透第二阱区域上的场绝缘膜和源极接触孔。