公开(公告)号：US20220384257A1

公开(公告)日：2022-12-01

申请号：US17887045

申请日：2022-08-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160093499A1

公开(公告)日：2016-03-31

申请号：US14869988

申请日：2015-09-29

Applicant: Renesas Electronics Corporation

Inventor： Kazuharu YAMABE ,  Shinichiro ABE ,  Shoji YOSHIDA ,  Hideaki YAMAKOSHI ,  Toshio KUDO ,  Seiji MURANAKA ,  Fukuo OWADA ,  Daisuke OKADA

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/28194 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract translation: 提供具有改进性能的半导体器件，同时提高半导体器件的制造步骤中的吞吐量。 在半导体衬底上形成由第一，第二，第三，第四和第五绝缘膜构成的绝缘膜部分。 第二绝缘膜是第一电荷存储膜，第四绝缘膜是第二电荷存储膜。 第一电荷储存膜含有硅和氮; 第三绝缘膜含有硅和氧; 并且第二电荷储存膜含有硅和氮。 第三绝缘膜的厚度小于第一电荷存储膜的厚度，并且第二电荷存储膜的厚度大于第一电荷存储膜的厚度。 第三绝缘膜通过用含水处理液处理第一电荷存储膜的上表面而形成。

公开(公告)号：US20200035552A1

公开(公告)日：2020-01-30

申请号：US16592869

申请日：2019-10-04

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20170040212A1

公开(公告)日：2017-02-09

申请号：US15298302

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract translation: 提高了半导体器件的性能。 在一个实施例中，例如，沉积时间从4.6秒增加到6.9秒。 换句话说，在一个实施例中，通过增加沉积时间来增加氮化钽膜的厚度。 具体地，在一个实施例中，沉积时间增加，使得设置在要连接到宽互连件的连接孔的底部上的氮化钽膜具有在5至10nm的范围内的厚度。

公开(公告)号：US20200251385A1

公开(公告)日：2020-08-06

申请号：US16854957

申请日：2020-04-22

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285 ,  C23C14/34 ,  C23C14/16 ,  C23C14/06

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160079188A1

公开(公告)日：2016-03-17

申请号：US14952618

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Kazuhito ICHINOSE ,  Seiji MURANAKA ,  Kazuyuki OMORI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/564 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.

公开(公告)号：US20180240700A1

公开(公告)日：2018-08-23

申请号：US15953948

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  C23C14/06 ,  H01L21/285 ,  C23C14/16 ,  C23C14/34

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20180090597A1

公开(公告)日：2018-03-29

申请号：US15657670

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Seiji MURANAKA

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/45 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L29/66545 ,  H01L21/02068 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/31053 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/67057 ,  H01L21/67086 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517

Abstract: The reliability of a semiconductor device is improved. A first gate electrode of a dummy gate electrode including silicon is formed over a semiconductor substrate. Then, by an ion implantation method, a semiconductor region for source or drain of MISFET is formed in the semiconductor substrate. Then, over the semiconductor substrate, an insulation film is formed in such a manner as to cover the first gate electrode. Then, the insulation film is polished to expose the first gate electrode. Then, the surface of the first gate electrode is wet etched by APM. then, the first gate electrode is removed by wet etching using aqueous ammonia. Thereafter, a gate electrode for MISFET is formed in a region from which the first gate electrode has been removed.

公开(公告)号：US20160163666A1

公开(公告)日：2016-06-09

申请号：US14952468

申请日：2015-11-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akira YAJIMA ,  Seiji MURANAKA

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/023 ,  H01L2224/02317 ,  H01L2224/024 ,  H01L2224/033 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/4807 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/85345 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20753 ,  H01L2224/45157 ,  H01L2924/00

Abstract: To improve an integration degree of a semiconductor device.The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.

Abstract translation: 提高半导体器件的集成度。 半导体器件包括形成在半导体衬底上的多个布线层，形成在多个布线层中的最上布线层上的焊盘电极，在焊盘电极上方具有焊盘开口的基底绝缘膜，以及电连接到 焊盘电极并在基底绝缘膜上延伸。 此外，半导体器件包括覆盖重新布线的上表面的保护膜，并且具有暴露重新布线的上表面的一部分的外部焊盘开口，外部焊盘电极通过外部焊盘开口电连接到重新布线并且延伸越过 保护膜和连接到外部焊盘电极的电线。 外部焊盘电极的一部分位于重新布线之外的区域中。