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    Uniform batch film deposition process and films so produced
    1.
    发明申请
    Uniform batch film deposition process and films so produced 审中-公开
    均匀分批膜沉积工艺和薄膜如此生产

    公开(公告)号：US20070010072A1

    公开(公告)日：2007-01-11

    申请号：US11482887

    申请日：2006-07-07

    申请人： Robert Bailey ,  Taiqing Qiu ,  Cole Porter ,  Olivier Laparra ,  Robert Chatham ,  Martin Mogaard ,  Helmuth Treichel

    发明人： Robert Bailey ,  Taiqing Qiu ,  Cole Porter ,  Olivier Laparra ,  Robert Chatham ,  Martin Mogaard ,  Helmuth Treichel

    IPC分类号： H01L21/20

    CPC分类号： C23C16/54 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45504 ,  C23C16/45578 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185

    摘要： A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant. A process for forming such a batch of wafer substrates involves feeding the precursor into a reactor containing a batch of wafer substrates and reacting the precursor at a wafer substrate temperature, total pressure, and precursor flow rate sufficient to create such a layer of material. The delivery of a precursor and co-reactant as needed through vertical tube injectors having multiple orifices with at least one orifice in registry with each of the batch of wafer substrates and exit slits within the reactor to create flow across the surface of each of the wafer substrates in the batch provides the within-wafer and wafer-to-wafer uniformity.

    摘要翻译： 一批晶片基板设置有每个晶片基板具有表面。 每个表面涂覆有同时施加到每批晶片衬底的表面的一层材料。 该材料层被施加到在整个表面上变化小于四个厚度百分比的厚度，而不是边缘边界，并且晶片到晶片的厚度变化小于3％。 如此施加的材料层是氧化硅，氮化硅或氮氧化硅，其中该材料层不含碳和氯。 氧化硅或氮氧化硅的形成需要包含共反应物。 氮化氮也通过包含硝化共反应物形成。 用于形成这样一批晶片衬底的方法包括将前体进料到含有一批晶片衬底的反应器中，并在足以产生这种材料层的晶片衬底温度，总压力和前体流速下使前体反应。 根据需要通过具有多个孔的垂直管注射器输送前体和共反应物，其中至少一个孔与反应器内的每批晶片基板和出口狭缝对齐，以产生跨过每个晶片的表面的流动 该批次中的衬底提供了晶片内和晶片与晶片之间的均匀性。

    Silicon corner rounding in shallow trench isolation process
    3.
    发明授权
    Silicon corner rounding in shallow trench isolation process 失效
    硅角圆化在浅沟槽隔离过程中

    公开(公告)号：US5811346A

    公开(公告)日：1998-09-22

    申请号：US837161

    申请日：1997-04-14

    申请人： Harlan Sur ,  Olivier Laparra ,  Dipankar Pramanik

    发明人： Harlan Sur ,  Olivier Laparra ,  Dipankar Pramanik

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H07L21/76

    CPC分类号： H01L21/76232 ,  Y10S148/05

    摘要： A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer. Thus, the present invention eliminates the sharp upper corners associated with prior art shallow trench isolation methods.

    摘要翻译： 一种用于形成这种结构的半导体器件隔离结构和方法。 在一个实施例中，通过覆盖半导体衬底的掩模层形成开口。 然后在掩模层中的开口下方的半导体衬底的区域处将期望深度的沟槽蚀刻到半导体衬底中。 然后用电介质材料填充沟槽。 在氧化物平面化处理之后，本发明将电介质填充的沟槽暴露于氧化环境。 通过在氧化步骤之前用电介质材料填充沟槽，本发明在由沟槽的侧壁和半导体衬底的顶表面的相交处形成的拐角处选择性地氧化半导体衬底。 这样做，本发明在掩模层下形成平滑的圆形半导体衬底拐角。 因此，本发明消除了与现有技术的浅沟槽隔离方法相关联的尖锐的上角。

    Manufacture of an integrated circuit isolation structure
    5.
    发明授权
    Manufacture of an integrated circuit isolation structure 有权
    制造集成电路隔离结构

    公开(公告)号：US06319796B1

    公开(公告)日：2001-11-20

    申请号：US09377043

    申请日：1999-08-18

    申请人： Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

    发明人： Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  Y10S148/05

    摘要： Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

    摘要翻译： 公开了提供集成电路的技术，包括提供改进的集成电路隔离结构。 这些技术包括在集成电路衬底中形成多个沟槽以限定要彼此电绝缘的多个衬底区域。 通过暴露于具有第一沉积到蚀刻比的高密度等离子体，在沟槽中沉积电介质材料。 将高密度等离子体调整到大于第一比率的第二沉积蚀刻比，以在至少部分地填充沟槽之后在基板上积累电介质材料。 去除介电材料的一部分以使工件平坦化。 可以随后在沟槽之间的衬底区域中形成多个组件，例如绝缘栅场效应晶体管。

    Removal of silicon oxynitride material using a wet chemical process after gate etch processing
    7.
    发明授权
    Removal of silicon oxynitride material using a wet chemical process after gate etch processing 失效
    在栅极蚀刻处理之后使用湿化学工艺去除氮氧化硅材料

    公开(公告)号：US06727166B1

    公开(公告)日：2004-04-27

    申请号：US09441899

    申请日：1999-11-17

    申请人： Edward Yeh ,  Olivier Laparra

    发明人： Edward Yeh ,  Olivier Laparra

    IPC分类号： H01L213205

    CPC分类号： H01L21/76224 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/3143 ,  H01L21/32137 ,  H01L21/32139

    摘要： A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the gate material. The layer of silicon oxynitride, the gate material and the gate oxide layer are etched to form a gate structure. A silicon oxynitride region remains on top of the gate structure. A wet chemical process is performed to remove the silicon oxynitride region from the top of the gate structure. After performing the wet chemical process, spacers are formed around the gate structure.

    摘要翻译： 提出了一种用于形成晶体管栅极结构的方法。 形成栅氧化层。 栅极材料沉积在栅极氧化物层上。 一层氮氧化硅沉积在栅极材料上。 氧氮化硅层，栅极材料和栅极氧化物层被蚀刻以形成栅极结构。 氮氧化硅区域保留在栅极结构的顶部。 执行湿式化学处理以从栅极结构的顶部去除氧氮化硅区域。 在执行湿式化学处理之后，在栅极结构周围形成间隔物。

    Trench-diffusion corner rounding in a shallow-trench (STI) process
    8.
    发明授权
    Trench-diffusion corner rounding in a shallow-trench (STI) process 有权
    沟槽扩散角在浅沟（STI）过程中四舍五入

    公开(公告)号：US06326283B1

    公开(公告)日：2001-12-04

    申请号：US09519908

    申请日：2000-03-07

    申请人： Victor Liang ,  Olivier Laparra ,  Mark Rubin

    发明人： Victor Liang ,  Olivier Laparra ,  Mark Rubin

    IPC分类号： H01L2176

    CPC分类号： H01L21/76235

    摘要： An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.

    摘要翻译： 使用浅沟槽隔离工艺形成集成电路上的隔离结构。 在衬底上形成一层缓冲氧化物。 在缓冲氧化物层上形成一层氮化物。 图案化氮化物层和缓冲氧化物层以形成沟槽区域。 执行衬底的氧化以在沟槽区域的周边提供圆角。 然后蚀刻衬底以在沟槽区域内形成沟槽。

    Soft edge induced local oxidation of silicon
    9.
    发明授权
    Soft edge induced local oxidation of silicon 失效
    软边缘引起硅的局部氧化

    公开(公告)号：US5920787A

    公开(公告)日：1999-07-06

    申请号：US783312

    申请日：1997-01-15

    申请人： Jake Haskell ,  Olivier Laparra ,  Jie Zheng

    发明人： Jake Haskell ,  Olivier Laparra ,  Jie Zheng

    IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/02164 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/76202 ,  H01L21/76235 ,  Y10S148/05

    摘要： A semiconductor device isolating structure and method for forming such a structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall extending to the bottom surface of the trench, and a second sidewall extending to the bottom surface of the trench. Furthermore, the trench of the present invention also has a first field oxide region formed proximate to the interface of the first sidewall and the top surface of the semiconductor substrate, and a second field oxide region formed proximate to the interface of the second sidewall and the top surface of the semiconductor substrate. As a result, the semiconductor substrate has a first rounded corner formed at the intersection of the top surface of semiconductor substrate and the first sidewall, and a second rounded corner formed at the intersection of the top surface of the semiconductor substrate and the second sidewall. In so doing, the present invention eliminates the sharp upper corners found in conventional trenches formed using prior art shallow trench isolation methods.

    摘要翻译： 一种用于形成这种结构的半导体器件隔离结构和方法。 在一个实施例中，本发明的半导体器件隔离结构包括形成半导体衬底的沟槽。 沟槽的横截面具有延伸到沟槽的底表面的第一侧壁和延伸到沟槽的底表面的第二侧壁。 此外，本发明的沟槽还具有靠近第一侧壁和半导体衬底的顶表面的界面形成的第一场氧化物区域，以及靠近第二侧壁和第二侧壁的界面形成的第二场氧化物区域 半导体衬底的顶表面。 结果，半导体衬底具有形成在半导体衬底的顶表面和第一侧壁之间的交叉点处的第一圆角和形成在半导体衬底的顶表面和第二侧壁的交叉处的第二圆角。 在这样做时，本发明消除了使用现有技术的浅沟槽隔离方法形成的常规沟槽中发现的尖锐的上角。