摘要:
In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
摘要:
Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability. A portion of the chips and substrate molding material may be removed after the substrate molding material is hardened.
摘要:
Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability. A portion of the chips and substrate molding material may be removed after the substrate molding material is hardened.
摘要:
By employing High Density Interconnect (HDI) multi-chip modules (MCMs) having elements of a distributed power supply embedded in the MCM itself, the functions of an MCM and a power converter are combined. The embedded power supply elements include DC-DC or AC-DC converters to convert an input voltage and input current to a relatively lower output voltage and relatively higher output current, thereby decreasing the current requirements of external power supply lines connected to the multi-chip module. The current and voltage outputs may be connected to chip power inputs through relatively short, low-impedance power distribution conductors comprising copper strips direct bonded to a ceramic substrate; alternatively, or in combination with direct bonded copper conductors, the low-impedance power distribution conductors may be situated within an HDI overcoat structure. The power supply elements may be placed within cavities formed in the substrate, or on a thinner portion of the substrate. The power supply may also provide multiple output voltages.
摘要:
A hermetic semiconductor chip package includes a conductive foil bonded to a contact pad of the chip and connected to an external lead of the package through an aperture in the insulating material of the package lid.
摘要:
A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer for interconnecting a circuit chip supported by a substrate and the use as printed circuit board material.
摘要:
A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer for interconnecting a circuit chip supported by a substrate and the use as printed circuit board material.
摘要:
An electronic structure includes a circuit chip having chip pads and supported by a substrate, and a low dielectric constant porous polymer layer having pores and situated over the substrate and circuit chip. The porous polymer layer has at least one via therein aligned with at least one of the chip pads, and a pattern of electrical conductors extends over a portion of the porous polymer layer and into the at least one via. The pattern of electrical conductors does not significantly protrude into the pores of the porous polymer layer.
摘要:
A mission planner system for a powered system, the mission planner system including a receiving device to collect aspect information as the powered system performs a mission, said aspect information being received from a remote location, a processor to determine a speed limit based at least in part on the aspect information, and a control system connected to the powered system to operate the powered system in response to the speed limit. A method and a computer software code for determining the mission plan with aspect information obtained from a remote location during the mission are also disclosed.
摘要:
A method for communicating on a train that has at least two locomotives, the method including determining when a primary communication path ceases to be available for a specific subsystem of the train, identifying at least one auxiliary communication path to transmit information for the specific subsystem, configuring a message for the specific subsystem which complies with a message format of the at least one auxiliary communication path, and transmitting the message on the at least one auxiliary communication path. A system and a computer software code are further disclosed for providing a communication system for a powered system.