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公开(公告)号：US5366906A
公开(公告)日：1994-11-22
申请号：US962000
申请日：1992-10-16
申请人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
发明人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
IPC分类号： G01R31/3185 , H01L21/301 , H01L21/66 , H01L23/538 , H01L23/58 , G01R31/26
CPC分类号： H01L22/22 , H01L22/32 , H01L23/5389 , H01L24/24 , H01L24/82 , G01R31/318505 , G01R31/318533 , H01L2224/2402 , H01L2224/24137 , H01L2224/24227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/351
摘要： In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
摘要翻译： 在制造晶片级集成互连件时，使用临时或永久的电介质层和电导体图案来提供晶片级整合或测试和老化。 可以使用抗蚀剂来覆盖晶片上的IC焊盘的区域，而去除电导体图案的其余部分以提供晶片级整合结构的修复。 电导体的图案可以被配置为使得在多个晶片上的至少一些子电路之间的导体长度对于信号传播目的而基本上是电相等的; 可以使用粘合剂将另外的晶片层压到晶片上; 受控的曲折可以被切入晶片; 并且晶片可以互连到接口环。
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公开(公告)号：US4901136A
公开(公告)日：1990-02-13
申请号：US285363
申请日：1988-12-15
申请人： Constantine A. Neugebauer , Lionel M. Levinson , Homer H. Glascock, II , Charles W. Eichelberger , Robert J. Wojnarowski , Richard O. Carlson
发明人： Constantine A. Neugebauer , Lionel M. Levinson , Homer H. Glascock, II , Charles W. Eichelberger , Robert J. Wojnarowski , Richard O. Carlson
IPC分类号： H01L23/04 , H01L23/495 , H01L23/538 , H01L25/065
CPC分类号： H01L23/5383 , H01L23/04 , H01L23/49541 , H01L23/5389 , H01L25/0655 , H01L2924/0002 , H01L2924/01079
摘要： A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.
摘要翻译： 一种用于将多个集成电路芯片互连到功能单元的封装，该功能单元包括具有接地和功率传导层的多层基板和用于将其端子焊盘保持在与基板相对的一侧的端子焊盘的框架。 芯片上的电源和接地端子焊盘通过记录穿过框架并进入衬底的导电馈通件与基板中适当的电源或导电层接触而耦合到适当的电位。 芯片上的信号焊盘通过位于与衬底相对的框架侧上的芯片上方的导电层相互连接。
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3.发明授权High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip 失效高电流密封包装，包括内部箔片，并且具有延伸穿过封装盖的引线和封装的半导体芯片
公开(公告)号：US5018002A
公开(公告)日：1991-05-21
申请号：US375641
申请日：1989-07-03
IPC分类号： H01L23/049 , H01L23/482 , H01L23/485
CPC分类号： H01L24/10 , H01L23/049 , H01L23/482 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1306 , H01L2924/14 , H01L2924/15787 , H01L2924/30107
摘要： A hermetic semiconductor chip package includes a conductive foil bonded to a contact pad of the chip and connected to an external lead of the package through an aperture in the insulating material of the package lid.
摘要翻译： 密封半导体芯片封装包括接合到芯片的接触焊盘并通过封装盖的绝缘材料中的孔连接到封装的外部引线的导电箔。
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4.发明授权
公开(公告)号：US5206186A
公开(公告)日：1993-04-27
申请号：US950553
申请日：1992-09-25
IPC分类号： H01L21/603 , H01L23/482
CPC分类号： H01L24/80 , H01L23/4827 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1301 , H01L2924/14 , H01L2924/30107
摘要： Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.
摘要翻译： 退火铜箔（12）涂覆有铬膜（16），然后用适当厚度的金膜（14）涂覆，并且热压粘合到硅芯片（30）上的铝金属化基板（18）上以提供可焊接 ，高电流接触芯片。 箔形成适当的电网接触图案（40），并且仅在芯片上存在铝金属化的情况下结合到硅芯片。 箔的翼（翼）部分（46）延伸超过硅芯片的边界，用于随后在箔上的后向反射以在预先指定的位置（49）提供电接触。 通过穿过位于箔区域正上方的陶瓷盖制成与箔的外部接触。 因此，主要铜箔与铝半导体焊盘的直接热压接可以通过金属间AuAl2连接和铝层将铜导体固定在硅芯片上来取代当前的金制定位/凸点连接。
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5.发明授权Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip 失效形成具有延伸穿过封装盖中的孔的引线和封装的半导体芯片的密封封装的方法
公开(公告)号：US5135890A
公开(公告)日：1992-08-04
申请号：US765286
申请日：1991-09-25
申请人： Victor A. K. Temple , Donald L. Watrous , Constantine A. Neugebauer , James F. Burgess , Homer H. Glascock, II
发明人： Victor A. K. Temple , Donald L. Watrous , Constantine A. Neugebauer , James F. Burgess , Homer H. Glascock, II
IPC分类号： H01L23/04 , H01L23/049 , H01L23/485
CPC分类号： H01L24/10 , H01L23/04 , H01L23/049 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/1301 , H01L2924/1306 , H01L2924/14 , H01L2924/15787 , H01L2924/30107
摘要： A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.
摘要翻译： 用于半导体器件的密封封装包括一个盖子，该器件的引线通过该盖子通过盖子的孔垂直地远离芯片延伸，盖子上的孔被外部端子或电极气密地密封。 该包装体积小巧，重量轻，无磁性材料。
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公开(公告)号：US5100740A
公开(公告)日：1992-03-31
申请号：US777495
申请日：1991-10-15
IPC分类号： B23K35/00 , C04B37/02 , H01L21/48 , H01L23/492 , H01L23/498
CPC分类号： H01L23/49866 , B23K35/001 , C04B37/021 , C04B37/026 , H01L21/4839 , H01L21/4871 , H01L23/4922 , C04B2237/06 , C04B2237/124 , C04B2237/34 , C04B2237/343 , C04B2237/403 , C04B2237/407 , C04B2237/62 , C04B2237/72 , C04B2237/82 , C04B2237/86 , H01L2924/0002 , H01L2924/09701 , Y10T428/12535 , Y10T428/12542 , Y10T428/1259 , Y10T428/12611 , Y10T428/12826 , Y10T428/1284 , Y10T428/12903
摘要： A composite structure comprising a symmetric bimetallic laminate bonded to a separate substrate is provided by eutectic bonding the bimetallic laminate to the substrate. A variety of beneficial structures can be provided.
摘要翻译： 通过将双金属层压体共晶接合到基底上来提供包含结合到单独基底的对称双金属层压板的复合结构。 可以提供各种有益的结构。
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公开(公告)号：US4996116A
公开(公告)日：1991-02-26
申请号：US454547
申请日：1989-12-21
CPC分类号： B32B15/018 , H05K1/0306 , H05K3/38 , Y10T428/12576 , Y10T428/12611 , Y10T428/1266 , Y10T428/12833 , Y10T428/12868 , Y10T428/12875 , Y10T428/12889 , Y10T428/12903
摘要： A direct (metal-metal compound eutectic) bond process is improved by disposing a eutectic/substrate-wetting enhancement layer on the substrate prior to performing the direct bond process to bond a metal foil to the substrate. Where the metal is copper, the direct bond process is rendered more effective than prior art direct bond processes on alumina and beryllia and makes the direct bond process effective on tungsten, molybdenum and aluminum nitride, all of which were unusable with the prior art direct bond copper process. A variety of new, useful structures may be produced using this process. The eutectic/substrate-wetting enhancement layer is preferably a noble-like metal or includes a noble-like metal such as platinum, palladium and gold.
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8.发明授权
公开(公告)号：US4769744A
公开(公告)日：1988-09-06
申请号：US851275
申请日：1986-04-10
CPC分类号： H01L24/06 , H01L23/32 , H01L24/72 , H01L2224/05554 , H01L2224/48091 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15173 , H01L2924/16152 , H01L2924/351
摘要： Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it fails due to increased thermal resistance arising from structural degradation of the solder layers.
摘要翻译： 半导体芯片封装中的用于电连接到半导体芯片上的电极的导电的导体的焊料层受到超过约2磅/平方英寸的横向压缩力。 由于由于焊料层的结构劣化引起的耐热性增加，因此半导体芯片封装在其失效之前的加热和冷却循环次数显着增加。
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公开(公告)号：US4750666A
公开(公告)日：1988-06-14
申请号：US853255
申请日：1986-04-17
IPC分类号： B23K20/00 , H01L21/00 , H01L23/485 , B23K31/02
CPC分类号： H01L24/13 , B23K20/007 , H01L24/11 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/05669 , H01L2224/13099 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48669 , H01L2224/48724 , H01L2224/48744 , H01L2224/48769 , H01L2224/78301 , H01L2224/85201 , H01L2224/85205 , H01L24/45 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01024 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/14
摘要： A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.
摘要翻译： 用于在半导体芯片的金属化焊盘上沉积金凸块的方法使用市售的热压或热镍金线焊接机。 该方法包括以下步骤：在金属化焊盘上沉积附有金属线的金球，并且去除金属丝，使得焊盘上留下金凸块。
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公开(公告)号：US5304847A
公开(公告)日：1994-04-19
申请号：US7300
申请日：1993-01-21
IPC分类号： H01L21/60 , H01L21/603 , H01L23/482 , H01L23/48 , H01L29/40
CPC分类号： H01L24/80 , H01L23/4827 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1301 , H01L2924/14 , H01L2924/30107
摘要： Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.
摘要翻译： 退火铜箔（12）涂覆有铬膜（16），然后用适当厚度的金膜（14）涂覆，并且热压粘合到硅芯片（30）上的铝金属化基板（18）上以提供可焊接 ，高电流接触芯片。 箔形成适当的电网接触图案（40），并且仅在芯片上存在铝金属化的情况下结合到硅芯片。 箔的翼（翼）部分（46）延伸超过硅芯片的边界，用于随后在箔上的后向反射以在预先指定的位置（49）提供电接触。 通过穿过位于箔区域正上方的陶瓷盖制成与箔的外部接触。 因此，主要铜箔与铝半导体焊盘的直接热压接可以通过金属间AuAl2连接和铝层将铜导体固定在硅芯片上来取代当前的金制定位/凸点连接。
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