公开(公告)号：US20110060865A1

公开(公告)日：2011-03-10

申请号：US12772005

申请日：2010-04-30

申请人： Robert W. Warren ,  David L. Dreifus ,  Robert E. Ober

发明人： Robert W. Warren ,  David L. Dreifus ,  Robert E. Ober

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/1036 ,  G06F2212/222 ,  G06F2212/7203

摘要： Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a non-volatile memory, a flash memory, and a read/write controller circuit. The read/write controller circuit is coupled to both the flash memory and the non-volatile memory, and is operable to receive a data set directed to the flash memory and to direct the data set to the random access memory.

摘要翻译： 本发明的各种实施例提供用于存储器及其利用的系统，方法和电路。 作为一个示例，公开了包括非易失性存储器，闪速存储器和读/写控制器电路的存储器系统。 读/写控制器电路耦合到闪速存储器和非易失性存储器，并且可操作以接收指向闪速存储器的数据集并将数据集引导到随机存取存储器。

公开(公告)号：US20100306580A1

公开(公告)日：2010-12-02

申请号：US12473437

申请日：2009-05-28

申请人： Brian D. McKean ,  David L. Dreifus ,  Robert W. Warren

发明人： Brian D. McKean ,  David L. Dreifus ,  Robert W. Warren

IPC分类号： G06F11/20 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G11C16/349 ,  G11C29/76

摘要： Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.

摘要翻译： 本发明的各种实施例提供用于数据存储的系统和方法。 作为示例，公开了包括多个存储块，不可靠块识别电路和部分故障指示电路的存储设备。 多个存储块中的每一个包括多个存储单元，随着访问时存储单元的可靠性随着时间的推移而降低。 所述不可靠块识别电路可操作以确定所述多个存储器块中的一个或多个不可靠，并且所述部分故障指示电路可操作以在确定所述多个存储块中的数量不足的情况下不允许对所述多个存储器块的写入访问 内存块保持可靠。

公开(公告)号：US20100306577A1

公开(公告)日：2010-12-02

申请号：US12473454

申请日：2009-05-28

申请人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

发明人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

IPC分类号： G06F12/16 ,  G06F11/14 ,  G06F11/16 ,  G06F12/00 ,  G06F12/02

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C16/349

摘要： Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

摘要翻译： 本发明的各种实施例提供了用于管理固态驱动器的系统和方法。 作为示例，描述了包括至少第一闪存块和第二闪存块以及控制电路的存储系统。 第一个闪存块和第二个闪存块在存储系统中是可寻址的。 控制电路可操作以将第一闪存块识别为部分故障，接收针对第一闪存块的写入请求; 并将写请求定向到第二闪存块。

公开(公告)号：US08745449B2

公开(公告)日：2014-06-03

申请号：US13347827

申请日：2012-01-11

申请人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

发明人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C16/349

摘要： Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

摘要翻译： 本发明的各种实施例提供了用于管理固态驱动器的系统和方法。 作为示例，描述了包括至少第一闪存块和第二闪存块以及控制电路的存储系统。 第一个闪存块和第二个闪存块在存储系统中是可寻址的。 控制电路可操作以将第一闪存块识别为部分故障，接收针对第一闪存块的写入请求; 并将写请求定向到第二闪存块。

公开(公告)号：US08151137B2

公开(公告)日：2012-04-03

申请号：US12473437

申请日：2009-05-28

申请人： Brian D. McKean ,  David L. Dreifus ,  Robert W. Warren

发明人： Brian D. McKean ,  David L. Dreifus ,  Robert W. Warren

IPC分类号： G06F11/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G11C16/349 ,  G11C29/76

摘要： Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.

摘要翻译： 本发明的各种实施例提供用于数据存储的系统和方法。 作为示例，公开了包括多个存储块，不可靠块识别电路和部分故障指示电路的存储设备。 多个存储块中的每一个包括多个存储单元，随着访问时存储单元的可靠性随着时间的推移而降低。 所述不可靠块识别电路可操作以确定所述多个存储器块中的一个或多个不可靠，并且所述部分故障指示电路可操作以在确定所述多个存储块中的数量不足的情况下不允许对所述多个存储器块的写访问 内存块保持可靠。

公开(公告)号：US08176367B2

公开(公告)日：2012-05-08

申请号：US12473454

申请日：2009-05-28

申请人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

发明人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C16/349

摘要： Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

摘要翻译： 本发明的各种实施例提供了用于管理固态驱动器的系统和方法。 作为示例，描述了包括至少第一闪存块和第二闪存块以及控制电路的存储系统。 第一个闪存块和第二个闪存块在存储系统中是可寻址的。 控制电路可操作以将第一闪存块识别为部分故障，接收针对第一闪存块的写入请求; 并将写请求定向到第二闪存块。

公开(公告)号：US20120110376A1

公开(公告)日：2012-05-03

申请号：US13347827

申请日：2012-01-11

申请人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

发明人： David L. Dreifus ,  Robert W. Warren ,  Brian McKean

IPC分类号： G06F11/00 ,  G06F12/02

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C16/349

摘要： Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

摘要翻译： 本发明的各种实施例提供了用于管理固态驱动器的系统和方法。 作为示例，描述了包括至少第一闪存块和第二闪存块以及控制电路的存储系统。 第一个闪存块和第二个闪存块在存储系统中是可寻址的。 控制电路可操作以将第一闪存块识别为部分故障，接收针对第一闪存块的写入请求; 并将写请求定向到第二闪存块。

公开(公告)号：US09054115B2

公开(公告)日：2015-06-09

申请号：US13311436

申请日：2011-12-05

申请人： Dinhphuoc V. Hoang ,  Thomas E. Noll ,  Anil K. Agarwal ,  Robert W. Warren ,  Matthew S. Read ,  Anthony LoBianco

发明人： Dinhphuoc V. Hoang ,  Thomas E. Noll ,  Anil K. Agarwal ,  Robert W. Warren ,  Matthew S. Read ,  Anthony LoBianco

IPC分类号： H01L21/56 ,  H05K3/36 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.

摘要翻译： 根据一个示例性实施例，包覆成型的包装包括位于基底上的部件。 包覆成型的包装进一步包括位于组件和衬底之上的包覆成型。 包覆成型的包装还包括位于衬底上方和覆盖模制件中的引线键合框架，其中引线键合框架围绕组件，并且其中引线键合框架包括多个引线键。 引线键盘在组件周围形成EMI屏蔽。 根据该示例性实施例，包覆成型的封装还包括位于包覆模制体的顶表面上并连接到引线键合框架的导电层，其中导电层在部件上形成EMI屏蔽。

公开(公告)号：US20130087915A1

公开(公告)日：2013-04-11

申请号：US13270012

申请日：2011-10-10

申请人： Robert W. Warren ,  Nic Rossi ,  Hyun Jung Lee

发明人： Robert W. Warren ,  Nic Rossi ,  Hyun Jung Lee

IPC分类号： H01L23/498 ,  H01L21/66 ,  H01L21/56

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/538 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/033 ,  H01L2224/03334 ,  H01L2224/03828 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/06177 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/48465 ,  H01L2224/48847 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L22/14 ,  H01L2223/544 ,  H01L21/78 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.

摘要翻译： 提供了一种用于铜柱凸起晶片级封装的系统和方法。 提供一种半导体封装，其包括在其顶表面上具有多个接合焊盘的半导体管芯，多个金属突起，其机械和电耦合到所述多个接合焊盘，以及多个焊球，机械地和电耦合到 所述多个金属柱凸起。 有利地，可以使用标准引线键合设备来提供金属柱凸块，避免用于光刻和沉积步骤的常规晶片级封装要求以提供多层金属布线结构。 因此，可以提供缩短的循环时间，降低成本和降低的复杂性。 使用金属柱凸块的替代制造工艺也可以支持具有来自不同晶片和封装的多管芯封装，其中芯片周边焊盘与衬底引线键合。

公开(公告)号：US20130062742A1

公开(公告)日：2013-03-14

申请号：US13230633

申请日：2011-09-12

申请人： Robert W. Warren ,  Nic Rossi

发明人： Robert W. Warren ,  Nic Rossi

IPC分类号： H01L23/495 ,  H01L21/28

CPC分类号： H01L24/05 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/37001 ,  H01L2924/37002 ,  H01L2224/05599 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds.

摘要翻译： 提供了一种用于铜线的阵列设计的点电镀引线框和IC焊盘的系统和方法。 提供了一种半导体封装，其包括在所述预镀完成时具有预镀整理和点镀的引线框，在其顶表面上包括接合焊盘的半导体管芯和与所述点电镀结合的铜线，以及 说粘合垫。 可选地，可以在接合焊盘下面提供新的角通孔阵列设计，以改善封装性能，同时保持铜线接合的完整性。 半导体封装可以提供几个优点，包括高MSL等级，简化的组装周期，避免锡晶须问题，以及与使用金线键的常规封装相比较低的成本。