公开(公告)号：US09029991B2

公开(公告)日：2015-05-12

申请号：US12927549

申请日：2010-11-16

申请人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

发明人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49503 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.

摘要翻译： 描述了具有减少的焊料空隙的示例性半导体封装，其具有具有I / O焊盘和热焊盘的引线框架，具有接合焊盘的制造的半导体管芯，其中所制造的半导体管芯附接到散热焊盘的顶表面 以及将接合焊盘连接到I / O焊盘的引线键合，其中散热焊盘的底表面具有通道。

公开(公告)号：US20120119341A1

公开(公告)日：2012-05-17

申请号：US12927549

申请日：2010-11-16

申请人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

发明人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L23/49503 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.

摘要翻译： 描述了具有减少的焊料空隙的示例性半导体封装，其具有具有I / O焊盘和热焊盘的引线框架，具有接合焊盘的制造的半导体管芯，其中所制造的半导体管芯附接到散热焊盘的顶表面 以及将接合焊盘连接到I / O焊盘的引线键合，其中散热焊盘的底表面具有通道。

公开(公告)号：US20130087915A1

公开(公告)日：2013-04-11

申请号：US13270012

申请日：2011-10-10

申请人： Robert W. Warren ,  Nic Rossi ,  Hyun Jung Lee

发明人： Robert W. Warren ,  Nic Rossi ,  Hyun Jung Lee

IPC分类号： H01L23/498 ,  H01L21/66 ,  H01L21/56

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/538 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/033 ,  H01L2224/03334 ,  H01L2224/03828 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/06177 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/48465 ,  H01L2224/48847 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L22/14 ,  H01L2223/544 ,  H01L21/78 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.

摘要翻译： 提供了一种用于铜柱凸起晶片级封装的系统和方法。 提供一种半导体封装，其包括在其顶表面上具有多个接合焊盘的半导体管芯，多个金属突起，其机械和电耦合到所述多个接合焊盘，以及多个焊球，机械地和电耦合到 所述多个金属柱凸起。 有利地，可以使用标准引线键合设备来提供金属柱凸块，避免用于光刻和沉积步骤的常规晶片级封装要求以提供多层金属布线结构。 因此，可以提供缩短的循环时间，降低成本和降低的复杂性。 使用金属柱凸块的替代制造工艺也可以支持具有来自不同晶片和封装的多管芯封装，其中芯片周边焊盘与衬底引线键合。

公开(公告)号：US20100213590A1

公开(公告)日：2010-08-26

申请号：US12713141

申请日：2010-02-25

申请人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

发明人： Robert W. Warren ,  Hyun Jung Lee ,  Nic Rossi

IPC分类号： H01L23/58 ,  H01L21/50

CPC分类号： H01L24/33 ,  H01L23/576 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.

摘要翻译： 阻挡层可以在半导体封装中附接到一个或多个敏感器件。 阻挡层可用于阻止恶意代理人尝试访问敏感设备上的敏感信息的篡改。 如果物理篡改，屏障层可能导致敏感设备变得不可操作。 保护性包装的其他方面提供了对X射线和热探测以及化学和电气篡改尝试的保护。

公开(公告)号：US09230928B2

公开(公告)日：2016-01-05

申请号：US13230633

申请日：2011-09-12

申请人： Robert W. Warren ,  Nic Rossi

发明人： Robert W. Warren ,  Nic Rossi

IPC分类号： H01L29/72 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L24/05 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/37001 ,  H01L2924/37002 ,  H01L2224/05599 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds.

摘要翻译： 提供了一种用于铜线的阵列设计的点电镀引线框和IC焊盘的系统和方法。 提供了一种半导体封装，其包括在所述预镀完成时具有预镀整理和点镀的引线框，在其顶表面上包括接合焊盘的半导体管芯和与所述点电镀结合的铜线，以及 说粘合垫。 可选地，可以在接合焊盘下面提供新的角通孔阵列设计，以改善封装性能，同时保持铜线接合的完整性。 半导体封装可以提供几个优点，包括高MSL等级，简化的组装周期，避免锡晶须问题，以及与使用金线键的常规封装相比较低的成本。

公开(公告)号：US20120032350A1

公开(公告)日：2012-02-09

申请号：US12852353

申请日：2010-08-06

申请人： Robert W. Warren ,  Jianjun Li ,  Nic Rossi

发明人： Robert W. Warren ,  Jianjun Li ,  Nic Rossi

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L23/3677 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

摘要翻译： 通过将接合线通过以线环形结构或柱状配置结合到接合焊盘来添加热导管可以改善制造的裸片的热耗散。 热导管可以作为半导体管芯的正常封装工艺的一部分加入，并且与制造的管芯上制造的电路电隔离。 替代地，将虚设的模具固定到制造的模具上，并且将热导管固定到虚设模具。 此外，热导管可以与散热器结合使用。

公开(公告)号：US20130062742A1

公开(公告)日：2013-03-14

申请号：US13230633

申请日：2011-09-12

申请人： Robert W. Warren ,  Nic Rossi

发明人： Robert W. Warren ,  Nic Rossi

IPC分类号： H01L23/495 ,  H01L21/28

CPC分类号： H01L24/05 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/37001 ,  H01L2924/37002 ,  H01L2224/05599 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds.

摘要翻译： 提供了一种用于铜线的阵列设计的点电镀引线框和IC焊盘的系统和方法。 提供了一种半导体封装，其包括在所述预镀完成时具有预镀整理和点镀的引线框，在其顶表面上包括接合焊盘的半导体管芯和与所述点电镀结合的铜线，以及 说粘合垫。 可选地，可以在接合焊盘下面提供新的角通孔阵列设计，以改善封装性能，同时保持铜线接合的完整性。 半导体封装可以提供几个优点，包括高MSL等级，简化的组装周期，避免锡晶须问题，以及与使用金线键的常规封装相比较低的成本。

公开(公告)号：US20110001230A1

公开(公告)日：2011-01-06

申请号：US12497241

申请日：2009-07-02

申请人： Jianjun Li ,  Robert W. Warren ,  Nic Rossi

发明人： Jianjun Li ,  Robert W. Warren ,  Nic Rossi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Adequate heat dissipation is essential for semiconductor devices. When a device exceeds a specified junction temperature, the device can be damaged, not perform correctly, or can have a reduced operating life. Semiconductor packages must dissipate heat from the chip to the external environment (i.e. to the PCB, air, etc) to keep the semiconductor device below a certain temperature threshold. For most devices, the most efficient way to dissipate the heat is through the package external I/O connections and into the PCB that it is mounted to. For Ball Grid Array (BGA) packages, the external I/Os are solder balls. Variable pitch packages pose advantages in heat dissipation without introducing significant costs.

摘要翻译： 充分的散热对于半导体器件至关重要。 当设备超过指定的结温时，设备可能会损坏，不能正常工作，或者可以减少使用寿命。 半导体封装必须从芯片向外部环境（即PCB，空气等）散热，以将半导体器件保持在一定的温度阈值以下。 对于大多数器件而言，耗散热量的最有效方式是通过封装外部I / O连接和安装到其中的PCB。 对于球栅阵列（BGA）封装，外部I / O是焊球。 可变间距封装在散热方面构成优势，而不会引起显着的成本。

公开(公告)号：US08552540B2

公开(公告)日：2013-10-08

申请号：US13104620

申请日：2011-05-10

申请人： Robert W. Warren ,  Nic Rossi

发明人： Robert W. Warren ,  Nic Rossi

IPC分类号： H01L23/495

CPC分类号： H01L23/3677 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/2732 ,  H01L2224/2746 ,  H01L2224/28105 ,  H01L2224/291 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00

摘要： Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

摘要翻译： 晶圆级封装（WLP）封装半导体管芯到晶片结构上。 在晶片级封装完成之后，通过单晶晶片级封装获得单个封装。 所得包装具有适合于小型化的小尺寸。 不幸的是传统的WLP散热差。 具有热焊盘的插入件可以附接到半导体管芯，以便于改善散热。 在一个实施例中，插入器还可以提供用于晶片级封装的晶片衬底。 此外，可以使用成熟且廉价的工艺来构建中介层。 附接到插入器的散热垫可以耦合到系统的接地平面，其中可以消散从半导体管芯吸收的热量。

公开(公告)号：US20120326304A1

公开(公告)日：2012-12-27

申请号：US13168605

申请日：2011-06-24

申请人： Robert W. Warren ,  Nic Rossi

发明人： Robert W. Warren ,  Nic Rossi

IPC分类号： H01L25/11 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/49582 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/206

摘要： There is provided a system and method for an externally wire bondable chip scale package in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad disposed thereon, a packaged device attached to the substrate, wherein an electrode of the packaged device is wirebonded to the first contact pad, and an unpackaged device, wherein an electrode of the unpackaged device is coupled to the substrate. By flipping the packaged device within the module and utilizing wire bondable finishes on the packaged device, an externally wire bondable chip scale package may be provided. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, a single assembly line, facilitated die substitution, reduced heat stress, higher package density, and a simplified single package structure for reduced fabrication time and cost.

摘要翻译： 提供了一种用于系统级封装模块中的外部可焊接芯片级封装的系统和方法。 提供了一种系统级封装模块，包括：衬底，其包括设置在其上的第一接触焊盘，附接到衬底的封装器件，其中封装器件的电极与第一接触焊盘引线接合，以及未封装器件，其中 未封装的器件的电极耦合到衬底。 通过翻转模块内的封装装置，并利用封装装置上的可焊线整理，可以提供外部可焊接芯片级封装。 所公开的系统级封装模块的结构提供了超过常规设计的几个优点，包括增加的产量，单个装配线，便于模具替代，降低的热应力，更高的封装密度和简化的单封装结构，以减少制造时间和成本 。